A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.

The present disclosure pertains to systems and methods for monitoring and protecting an electric power system. In one embodiment, a system may comprise line-mounted wireless current transformers to measure at least one parameter of an alternating current (AC), receive a synchronization signal at which to measure the AC, and send a message comprising the measured AC. The system may also comprise an intelligent electronic device (IED) to send the synchronization signal to and receive the messages from the line-mount wireless current transformers, determine whether a high-impedance fault (HiZ) exists between the line-mounted wireless current transformers, and implement a control action based on the existence of the HiZ fault.

The present disclosure pertains to systems and methods for monitoring and protecting an electric power system. In one embodiment, a system may comprise line-mounted wireless current transformers to measure at least one parameter of an alternating current (AC), receive a synchronization signal at which to measure the AC, and send a message comprising the measured AC. The system may also comprise an intelligent electronic device (IED) to send the synchronization signal to and receive the messages from the line-mount wireless current transformers, determine whether a high-impedance fault (HiZ) exists between the line-mounted wireless current transformers, and implement a control action based on the existence of the HiZ fault.

An automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.

An apparatus for performing scan test of IC chip includes a shift-frequency searching unit that searches usable shift frequency for a target scan section among at least one scan section each including whole or part of at least one scan pattern inputted to a scan path. When searching usable shift frequency for the target scan section, the shift-frequency searching unit scales shift frequency of the target scan section differently from that of at least one scan section among scan sections shifted before or after the target scan section or sets shift frequency of the target scan section differently from that of the at least one scan section among the scan sections shifted before or after the target scan section, and searches shift frequency with which result of the scan test indicates pass or shift frequency with which result of the scan test indicates fail.

An apparatus for performing a scan test of IC chip includes a shift-frequency searching unit that executes first scan test for first scan pattern whole or part of which constituting first scan section and second scan test for second scan pattern whole or part of which constituting second scan section, and searches usable shift frequency for the second scan section. The first scan pattern is scan pattern inputted to scan path right before the second scan pattern. The shift-frequency searching unit shifts the first scan section to the scan path with first shift frequency in the first scan test, shifts the second scan section to the scan path with second shift frequency in the second scan test, and determines, when both results of the first scan test and the second scan test indicate pass, the second shift frequency as the usable shift frequency for the second scan section.

An apparatus for performing a scan test of IC chip includes a shift-frequency searching unit that executes first scan test for first scan pattern whole or part of which constituting first scan section and second scan test for second scan pattern whole or part of which constituting second scan section, and searches usable shift frequency for the second scan section. The first scan pattern is scan pattern inputted to scan path right before the second scan pattern. The shift-frequency searching unit shifts the first scan section to the scan path with first shift frequency in the first scan test, shifts the second scan section to the scan path with second shift frequency in the second scan test, and determines, when both results of the first scan test and the second scan test indicate pass, the second shift frequency as the usable shift frequency for the second scan section.

An apparatus for performing a scan test of IC chip includes a shift-frequency searching unit that executes first scan test for first scan pattern whole or part of which constituting first scan section and second scan test for second scan pattern whole or part of which constituting second scan section, and searches usable shift frequency for the second scan section. The first scan pattern is scan pattern inputted to scan path right before the second scan pattern. The shift-frequency searching unit shifts the first scan section to the scan path with first shift frequency in the first scan test, shifts the second scan section to the scan path with second shift frequency in the second scan test, and determines, when both results of the first scan test and the second scan test indicate pass, the second shift frequency as the usable shift frequency for the second scan section.

An apparatus for performing scan test of IC chip includes a shift-frequency searching unit that searches usable shift frequency for a target scan section among at least one scan section each including whole or part of at least one scan pattern inputted to a scan path. When searching usable shift frequency for the target scan section, the shift-frequency searching unit scales shift frequency of the target scan section differently from that of at least one scan section among scan sections shifted before or after the target scan section or sets shift frequency of the target scan section differently from that of the at least one scan section among the scan sections shifted before or after the target scan section, and searches shift frequency with which result of the scan test indicates pass or shift frequency with which result of the scan test indicates fail.

An automatic test pattern generation-based circuit verification method, comprises determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first conjunctive normal form (CNF) based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.