Damage to a joint part of a terminal of an electronic component mounted on a substrate is detected. The substrate includes a base material unit, a land, and a light detection unit. The land included in the substrate is arranged with a stress light emitting body configured to emit light in accordance with stress, includes a transparent member, and is joined with a terminal of an element arranged in the base material unit included in the substrate. The light detection unit included in the substrate is arranged between the base material unit and the land included in the substrate, and detects light from the stress light emitting body.

A display device can include a display panel including a display area in which sub-pixels are disposed, and a non-display area adjacent to the display area and in which a second pad portion is disposed, a printed circuit board including a first pad portion for outputting voltages to the display panel, and a circuit film including a first end connected to the first pad portion of the printed circuit board and a second end connected to the second pad portion of the display panel. The display device can further include an analog-to-digital converter to receive a voltage output from the first pad portion or the second pad portion through a line in the circuit film electrically connecting the first pad portion with the second pad portion, and output a value corresponding to the voltage input for detecting a bonding state of at least one internal component within the display device.

The present disclosure relates to a concept for checking at least one solder joint between a printed circuit board and a current sensor, including: measuring, by means of the current sensor, an electric current through the solder joint; measuring at least one temperature of the current sensor as a function of the electric current; and ascertaining a quality of the solder joint based on the temperature and the electric current.

A system detects cracks in solder joints on a printed circuit board (PCB). The system includes a device, a signal generator, a termination resistor, and a detector. The device includes a first contact and a second contact coupled to the first contact. The device is soldered to the PCB by a first solder joint at the first contact and by a second solder joint at the second contact. The signal generator has a test signal output coupled to the first solder joint. The termination resistor has a first terminal coupled to the second solder joint, and a second terminal coupled to a ground plane of the PCB. The detector receives a reflected signal that is a reflection of the test signal from at least one of the first solder joint, the second solder joint, and the termination resistor. The detector provides an indication as to whether or not at least one of the first solder joint and the second solder joint is cracked based upon a magnitude of the reflected signal.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

A test system for an electrical system includes a slot array having a plurality of slots and a plurality of recesses formed therethrough, a plurality of mounts in which each mount of the plurality of mounts is positioned within a respective recess of the plurality of recesses to align with a respective slot of the plurality of slots, a connector port having a plurality of pins, and a plurality of conductors in which each conductor of the plurality of conductors extends from a respective pin of the plurality of pins to a respective mount of the plurality of mounts. Each mount of the plurality of mounts is configured to receive an additional conductor via a corresponding slot of the plurality of slots to electrically couple the additional conductor to a corresponding pin of the plurality of pins via a corresponding conductor of the plurality of conductors.

A test system for an electrical system includes a slot array having a plurality of slots and a plurality of recesses formed therethrough, a plurality of mounts in which each mount of the plurality of mounts is positioned within a respective recess of the plurality of recesses to align with a respective slot of the plurality of slots, a connector port having a plurality of pins, and a plurality of conductors in which each conductor of the plurality of conductors extends from a respective pin of the plurality of pins to a respective mount of the plurality of mounts. Each mount of the plurality of mounts is configured to receive an additional conductor via a corresponding slot of the plurality of slots to electrically couple the additional conductor to a corresponding pin of the plurality of pins via a corresponding conductor of the plurality of conductors.

A method for detecting errors or malfunctions in electrical or electronic components of circuits, wherein each of the circuits is located on a circuit board and wherein a plurality of circuit boards border one another on a circuit board panel, includes populating each of the circuit boards of the circuit board panel with electrical or electronic components corresponding to the circuits; for each of the analog, electrical or electronic components used for the construction of the circuits, placing a corresponding test component in an edge region of the circuit board panel; providing the analog, electrical or electronic test components placed in the edge region of the circuit board panel with test points; and checking for the correct function value and/or the correct poling of the analog, electrical or electronic test components provided with test points and located in the edge region of the circuit board panel.