An integrated circuit (IC) package comprising an optical die comprising a configurable optical switch. The configurable optical switch comprises an optical switch operably coupled to one or more optical transceivers. An optical connector comprises at least one exo-package optical port. The at least one exo-package optical port is operably coupled to the configurable optical switch. The configurable optical switch is to pass an optical signal on the at least one of the one or more exo-package ports to at least one of the one or more optical transceivers, and an IC die comprising electronic circuitry is operably coupled to the one or more optical transceivers.

A light conversion portion includes a conversion material that converts infrared light to visible light. A reflection portion is fixed to a position on a main substrate at which the reflection portion faces an output end of an optical waveguide chip on the side from which light is output to an external space. The reflection portion includes a reflection surface that faces the output end and is inclined with respect to a plane of the main substrate such that a reflection direction is toward the upper side of the main substrate. The reflection surface reflects near infrared light.

A balanced homodyne detection optical circuit according to the present disclosure is a planar optical waveguide circuit in which a circuit made of an optical waveguide including a dielectric or a semiconductor is formed on a substrate, the balanced homodyne detection optical circuit including an input port of local oscillator light and an input port of measurement light (squeezed light (including excitation light)), wherein a wavelength demultiplexing circuit which demultiplexes only the measurement light is arranged immediately after the input port of measurement light, a 50% multiplexing/demultiplexing circuit is arranged which causes squeezed light having been demultiplexed by the wavelength demultiplexing circuit and the local oscillator light to respectively branch at a branching ratio of 50% and to interfere with each other, and two output ports are arranged to which two outputs from the 50% multiplexing/demultiplexing circuit are guided.

A photonic integrated circuit (PIC) having a substrate in which vertically coupled photodetectors and in-line optical modulators are integrated to enable vertical coupling of light using a fiber assembly block (FAB), with the planar end surface thereof being attached to a substantially planar main surface of the substrate. In an example embodiment, the photodetectors are buried in deep vias formed in the substrate, and the in-line optical modulators are waveguide-connected to the corresponding vertical-coupling optical gratings. The photodetectors and optical gratings may be arranged in a linear array along the main surface of the substrate to enable uncomplicated optical alignment of end segments of the optical fibers in the FAB with the corresponding photodetectors and optical gratings for vertical coupling of light therebetween. In some embodiments, the FAB may have more than one hundred optical fibers. In some embodiments, the PIC can be implemented using the silicon photonics material platform.

Provided is a waveguide photodetector including a semiconductor substrate, a first optical waveguide and a second optical waveguide, which are sequentially laminated on the semiconductor substrate, in which each of the first optical waveguide and the second optical waveguide includes a first portion and a second portion, and the first portion extends from the second portion in a first direction parallel to a top surface of the semiconductor substrate, a refractive index matching layer disposed on the second portion of the second optical waveguide, a clad layer disposed on the refractive index matching layer, and an absorber disposed between the refractive index matching layer and the clad layer. Here, the second optical waveguide has a first conductive-type, the clad layer has a second conductive-type opposite to the first conductive-type, and the refractive index matching layer includes a first semiconductor layer that is an intrinsic semiconductor layer.

Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

In one embodiment, a silicon photonic integrated circuit (PIC) includes a pair of Mach-Zehnder Interferometers (MZI) with a phase shifter to function as a 1x2 optical switches. On one path between the MZIs is a wavelength interleaver. The MZI switch can be controlled to either an all-pass mode or a by-pass mode, therefore setting configurable optical demultiplexing bandwidths to support dual 1.6 T FR8/800G FR4 network backward compatibility. The configurable multiplexer operates at set-and-forget mode for the entire operating temperature and the product’s lifetime.

Arrayed waveguide gratings (AWGs) are important components in coarse wavelength divisional multiplexing (CWDM) and dense wavelength division multiplexing (DWDM). However, the waveguides forming the array must be separated by a distance large enough to suppress parasitic coupling between the adjacent waveguides and thus limiting reductions in device footprint and insertion loss between the input/output coupler regions and the central region comprising the arrayed waveguides. The inventors have established a design methodology allowing the waveguide separation to be reduced whilst limiting cross-coupling thereby allowing for reduced footprints and insertion loss.

Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

Disclosed are an optical phased array chip and a method of manufacturing the same. The optical phased array chip includes a plurality of optical switches and a plurality of optical phased arrays implemented on a single integrated circuit, wherein the single integrated circuit includes a silicon substrate, a lower layer formed on an upper portion of the silicon substrate, a silicon layer formed on an upper portion of the lower layer, a first upper layer, a second upper layer and a third upper layer sequentially arranged on the silicon layer, and an electrode that penetrates through the first upper layer while being grounded to the silicon layer and is formed on an upper portion of the first upper layer.