Structures for a grating coupler and methods of fabricating a structure for a grating coupler. The structure includes a grating coupler having a central portion and edge portions. The central portion and the edge portions define a sidewall, and the central portion and the edge portions have a first longitudinal axis along which the edge portions are arranged in a spaced relationship. Each edge portion projects from the sidewall at an angle relative to the first longitudinal axis. A waveguide core is optically coupled to the grating coupler. The first longitudinal axis is aligned in a first direction, and the waveguide core has a second longitudinal axis that is aligned in a second direction different from the first direction.

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

After a step of etching a core layer, a lower cladding layer, and a substrate so that a recessed opening including one end of an optical waveguide is formed relative to a multilayer board and a step of forming mask layers on a top surface of the substrate including the opening, in a step, crystal is grown with respect to the mask layers in the opening, and a tilt surface to be used as the monolithic mirror is formed. An upper cladding layer is formed covering the core layer at the same time. Then, formation of an optical waveguide pattern, formation of the optical waveguide and an end surface of the optical waveguide, formation of a dielectric film for preventing reflection, and formation of a metal film on a surface of the tilt surface are executed.

There is provided a method for fabricating a vertically tapered spot-size converter on a substrate, comprising: growing a waveguide core on the substrate; coating the waveguide core with a photoresist layer; placing a photomask having patterns at a negative focus offset point with respect to the photoresist layer, the patterns being defined by openings in the photomask, each opening having a cross-section comprising a region of constant width and at least one region of non-constant width, the non-constant width reducing in a direction extending away from the region of constant width; transferring the patterns of the photomask to the photoresist layer; providing the waveguide core with a vertically tapered profile, the vertically tapered profile being provided by the patterns of the photomask; growing a cladding layer over the waveguide core; and patterning and etching the cladding layer and the waveguide core, thereby defining the vertically tapered spot-size converter.

A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elements and/or active elements, the interface being produced on the surface of a second silicon-based substrate; removing the first silicon-based substrate and the at least elementary base layer located on the elementary structure.

There is set forth herein a method including building a first photonics structure using a first wafer having a first substrate, wherein the building the first photonics structure includes integrally fabricating within a first photonics dielectric stack one or more photonics device, the one or more photonics device formed on the first substrate; building a second photonics structure using a second wafer having a second substrate, wherein the building the second photonics structure includes integrally fabricating within a second photonics dielectric stack a laser stack structure active region and one or more photonics device, the second photonics dielectric stack formed on the second substrate; and bonding the first photonics structure and the second photonics structure to define an optoelectrical system having the first photonics structure bonded the second photonics structure.

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

A method of Silicon Selective Epitaxial Growth (SEG) applied to a Silicon on Insulator (SOI) wafer to provide a first region of customized thickness includes with the SOI wafer having a standard thickness, applying a hard mask to a plurality of regions of the SOI wafer including the first region; applying photo-lithography protection to cover the hard mask in all of the plurality of regions except the first region; removing the hard mask in the first region; and performing Silicon SEG in the first region to provide the customized thickness in the first region, wherein the customized thickness is greater than the standard thickness.

Structures for a photodetector or terminator and methods of fabricating a structure for a photodetector or terminator. The structure includes a waveguide core having a longitudinal axis, a pad connected to the waveguide core, and a light-absorbing layer on the pad adjacent to the waveguide core. The light-absorbing layer includes an annular portion, a first taper, and a second taper laterally spaced from the first taper. The first taper and the second taper are positioned adjacent to the waveguide core.

The invention relates to a method for fabricating a semiconductor structure. The method comprises fabricating a photonic crystal structure of a first material, in particular a first semiconductor material and selectively removing the first material within a predefined part of the photonic crystal structure. The method further comprises replacing the first material within the predefined part of the photonic crystal structure with one or more second materials by selective epitaxy. The one or more second materials may be in particular semiconductor materials. The invention further relates to devices obtainable by such a method.