G03F7/70658

OPTICALLY DETERMINING ELECTRICAL CONTACT BETWEEN METALLIC FEATURES IN DIFFERENT LAYERS IN A STRUCTURE
20230009177 · 2023-01-12 · ·

Optically determining whether metallic features in different layers in a structure are in electrical contact with each other. When the metallic features include different metals and/or have different dimensions, which cause one or more resonances in reflected radiation to be detected, the metallic features in the different layers are determined to be in contact or out of contact with each other based on the spectral positions of the one or more resonances. When the metallic features are formed from the same metal and have the same dimensions, the metallic features in the different layers are determined to be in contact with each other responsive to detection of a single resonance associated with the metallic features and out of contact with each other responsive to detection of two or more resonances associated with the metallic features.

MARK TO BE PROJECTED ON AN OBJECT DURING A LITHOGRAHPIC PROCESS AND METHOD FOR DESIGNING A MARK
20230229093 · 2023-07-20 · ·

The first layer mark and the second layer mark are adapted to be projected onto each other during the lithographic process. The first layer components and the second layer components are adapted to be arranged in a plurality of different overlay configurations, each overlay configuration comprising a number of the plurality of the first layer components and a number of the plurality of the second layer components, and each overlay configuration having a different overlay distance at which each first layer component is arranged in a first direction of an associated second layer component of the second layer components. The method comprises determining an overlay step which represents a difference between the different overlay distances of the plurality of overlay configurations, determining a largest overlay distance, determining the number of first layer components and/or the number of associated second layer components in each overlay configuration.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
20230010665 · 2023-01-12 · ·

A semiconductor structure includes vertical conductive features disposed over a substrate, and horizontal conductive features disposed over the vertical conductive features. The horizontal conductive features include first and second conductive lines respectively electrically connected to the first and second vertical conductive features, a first conductive segment disposed between the first vertical conductive feature and the second conductive line, and a second conductive segment disposed between the first conductive line and the second vertical conductive feature. The first conductive segment is electrically isolated from the vertical conductive features. The second conductive segment is electrically isolated from the vertical conductive features.

System and Method for Defect Classification Based on Electrical Design Intent

A method for automatically classifying one or more defects based on electrical design properties includes receiving one or more images of a selected region of a sample, receiving one or more sets of design data associated with the selected region of the sample, locating one or more defects in the one or more images of the selected region of the sample by comparing the one or more images of the selected region of the sample to the one or more sets of design data, retrieving one or more patterns of interest from the one or more sets of design data corresponding to the one or more defects, and classifying the one or more defects in the one or more images of the selected region of the sample based on one or more annotated electrical design properties included in the one or more patterns of interest.

Electrical measurable overlay structure

The wafer comprises a first line in a first layer of the wafer. The first line has a first terminal connected to the first line. The wafer comprises a second line in the first layer of the wafer. The second line has a second terminal connected to the second line. The second terminal has a probe connected to apply a voltage ramp. The wafer comprises a third line in the first layer of the wafer. The third line has a terminal connected to the third line.

PREDICTION OF ELECTRICAL PROPERTIES OF A SEMICONDUCTOR SPECIMEN
20220210525 · 2022-06-30 ·

There is provided a method and a system configured to obtain metrology data D.sub.metrology informative of a plurality of structural parameters of a semiconductor specimen, obtain a model informative of a relationship between at least some of said structural parameters and one or more electrical properties of the specimen, use the model and D.sub.metrology to determine, for at least one given electrical property of the specimen, one or more given structural parameters among the plurality of structural parameters, which affect the given electrical property according to an impact criterion, and generate a recipe for an examination tool, wherein the recipe enables a ratio between a first acquisition rate of data informative of the one or more given structural parameters, and a second acquisition rate of data informative of other structural parameters of the plurality of structural parameters, to meet a criterion.

Method to predict yield of a device manufacturing process

A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Efficient Semiconductor Metrology Using Machine Learning

A metrology system includes metrology equipment, a remote communication link, a local communication link, and a data processing unit (DPU). The metrology equipment is configured to generate a stream of data relating to inspected wafers, and to format the generated data into first and second data types. The remote communication link is configured to communicate with an external system. The data processing unit (DPU) is configured to (i) using the remote communication link, send the data belonging to the first data type directly to the external system, and (ii) perform analysis on the data belonging to the second data type, and, using the local communication link, provide results of the analysis to the metrology equipment.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, ARTICLE MANUFACTURING SYSTEM, AND ARTICLE MANUFACTURING METHOD
20220246456 · 2022-08-04 ·

An information processing apparatus includes an acquisition unit configured to acquire information including a processing result of processing a substrate by a substrate processing apparatus configured to perform substrate processing at a first timing, event information about an event having occurred in the substrate processing apparatus at a second timing after the first timing, and a processing result of processing the substrate by the substrate processing apparatus at a third timing after the second timing, and a display control unit configured to perform control so that a display device displays a chronological graph of a processing result including the processing result at the first timing and the processing result at the third timing based on the information acquired by the acquisition unit, wherein the display control unit performs control to display information in a superimposed manner on the graph, the information indicating the second timing.

A METHOD FOR CHARACTERIZING A MANUFACTURING PROCESS OF SEMICONDUCTOR DEVICES

A method of determining a characteristic of one or more processes for manufacturing features on a substrate, the method including: obtaining image data of a plurality of features on a least part of at least one region on a substrate; using the image data to obtain measured data of one or more dimensions of each of at least some of the plurality of features; determining a statistical parameter that is dependent on the variation of the measured data of one or more dimensions of each of at least some of the plurality of features; determining a probability of defective manufacture of features in dependence on a determined number of defective features in the image data; and determining the characteristic of the one or more processes to have the probability of defective manufacture of features and the statistical parameter.