An implantable medical device comprises an electronic functional device for performing a function of said implantable medical device, said electronic functional device having an operational state for performing said function and a switched-off state. A wake-up device serves for transferring said functional device from said switched-off state to said operational state. The wake-up device comprises a first timer circuit for repeatedly transferring the functional device to the operational state according to a predetermined first timing scheme, a detection device for detecting a signal from a signal source external to the implantable medical device, and a second timer circuit for repeatedly switching the detection device to a reception state according to a second timing scheme.

An implantable medical device comprises an electronic functional device for performing a function of said implantable medical device, said electronic functional device having an operational state for performing said function and a switched-off state. A wake-up device serves for transferring said functional device from said switched-off state to said operational state. The wake-up device comprises a first timer circuit for repeatedly transferring the functional device to the operational state according to a predetermined first timing scheme, a detection device for detecting a signal from a signal source external to the implantable medical device, and a second timer circuit for repeatedly switching the detection device to a reception state according to a second timing scheme.

An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.

An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.

A system for managing a time reference includes a real-time clock, an interface, and a processor. The real-time clock store an RTC time. The interface is configured to receive a GPS time and a cellular time. The processor is configured to: indicate to start a time-speed adjustment loop; determine a true time based at least in part on the GPS time and the cellular time; determine an error between the true time and the RTC time; determine an RTC speed calibration adjustment based at least in part on the error; and adjust the real-time clock speed based at least in part on the RTC speed calibration adjustment.

A system for managing a time reference includes a real-time clock, an interface, and a processor. The real-time clock store an RTC time. The interface is configured to receive a GPS time and a cellular time. The processor is configured to: indicate to start a time-speed adjustment loop; determine a true time based at least in part on the GPS time and the cellular time; determine an error between the true time and the RTC time; determine an RTC speed calibration adjustment based at least in part on the error; and adjust the real-time clock speed based at least in part on the RTC speed calibration adjustment.

A time synchronization method that is capable of selecting whether synchronization, by a timepiece unit that generates a time signal synchronized with a standard time and outputs it to an exterior, with the time is performed by time information obtained by receiving a radio wave including information relating to the time, or is performed by means of a holdover performed using a clock signal from an internal or external clock source. A schedule having a first time period in which the above-mentioned time information is used, and a second time period by means of the holdover is determined according to temporal reception characteristics of the radio wave at a reception location of the radio wave, and according to the schedule, supplying the timepiece unit with the time information or supplying the timepiece unit with the clock signal from the internal or external clock source.

A timepiece reduces power consumption while maintaining required precision. The timepiece has a frequency divider that frequency divides an oscillation signal and outputs a reference signal; nonvolatile memory that stores information related to a temperature characteristic of the oscillation frequency of the crystal oscillator; multiple registers; a temperature measuring circuit; an evaluation circuit; and a temperature compensation circuit. The temperature compensation circuit reads the information from one of the registers and corrects the reference signal based on the read information and the temperature measurement information when the evaluation circuit determines the information stored in the multiple registers is the same; and when the evaluation circuit determines the information stored in the multiple registers is different, reads the information from the nonvolatile memory, stores the read information in the multiple registers, and corrects the reference signal based on the read information and the temperature measurement information.

A timepiece reduces power consumption while maintaining required precision. The timepiece has a frequency divider that frequency divides an oscillation signal and outputs a reference signal; nonvolatile memory that stores information related to a temperature characteristic of the oscillation frequency of the crystal oscillator; multiple registers; a temperature measuring circuit; an evaluation circuit; and a temperature compensation circuit. The temperature compensation circuit reads the information from one of the registers and corrects the reference signal based on the read information and the temperature measurement information when the evaluation circuit determines the information stored in the multiple registers is the same; and when the evaluation circuit determines the information stored in the multiple registers is different, reads the information from the nonvolatile memory, stores the read information in the multiple registers, and corrects the reference signal based on the read information and the temperature measurement information.

A system for managing a time reference includes a real-time clock, an interface, and a processor. The real-time clock store an RTC time. The interface is configured to receive a GPS time and a cellular time. The processor is configured to: indicate to start a time-speed adjustment loop; determine a true time based at least in part on the GPS time and the cellular time; determine an error between the true time and the RTC time; determine an RTC speed calibration adjustment based at least in part on the error; and adjust the real-time clock speed based at least in part on the RTC speed calibration adjustment.