Digital logic voltage regulators and related methods generate a regulated voltage via controlled switching of a power transistor. A digital logic voltage regulator includes a voltage level comparator, a power transistor, and a charge accumulator. The voltage level comparator generates a digital control signal that alternates between a first voltage level and a second voltage level in response to changes in relative voltage level between the regulated output voltage and the target voltage. The digital control signal causes the power transistor to switch from off to on in response to a reduction of the regulated output voltage relative to the target voltage and causes the power transistor to switch from on to off in response to an increase of the regulated output voltage relative to the target voltage. The charge accumulator decreases variation in the regulated output voltage that would occur without the charge accumulator.

A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

A voltage adjustment apparatus, a chip, a power source, and an electronic device. The apparatus comprises: a voltage input module, used for receiving an input voltage; a current determining module, electrically connected to the voltage input module and used for determining an adjustment current on the basis of the input voltage and a load current; a control module, electrically connected to the current determining module and used for outputting a control signal on the basis of the adjustment current; and a voltage output module, electrically connected to the voltage input module, the current determining module, and the control module, and being used for outputting a target voltage on the basis of the control signal and the input voltage.

An aspect relates to an apparatus, including: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.

The present disclosure relates to a low-dropout regulator that limits a quiescent current. It mainly includes an error amplifier, an output switching transistor, a feedback switching transistor, a current duplicating circuit, and a clamping current source. The clamping current source is added between an input voltage and the feedback switching transistor, so that a feedback current outputted by the feedback switching transistor is clamped, and the highest value is only proportional to a current value of the clamping current source. In this way, the quiescent current outputted by the low-dropout regulator is no longer increasing indefinitely in proportional to a load current, which can effectively solve the technical problems of poor stability and decreased efficiency caused by the infinite increase of the quiescent current.

A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.

A sub-circuit of a voltage regulator includes a load condition detection circuit and a controllable circuit. The load condition detection circuit is arranged to detect a load transient frequency of a load powered by the voltage regulator, and generate a control signal according to a detection result of the load transient frequency. The controllable circuit is arranged to receive the control signal, wherein an operational behavior of the controllable circuit dynamically changes in response to the control signal.

A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.

A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.

A system, method and computer program product for operating a low-voltage Internet-of-Things sensor device. The method includes sensing of the temperature dependence at each voltage condition in addition to the actual temperature and voltage. A programmed machine learning model uses the information to decide when it is appropriate to test the device functionality and use the results of different tests to determine when the system should run synchronously or asynchronously through a machine learning predictive algorithm. Based on said one or more sensed operating conditions, the system uses the model to detect a mode of operation of said IoT device indicating IoT device meets an expected level of performance, or a mode indicating said IoT device is not operating according to the expected level of performance. Based on the detected operating condition, the IoT device automatically adapts its operation to ensure a desired level of IoT sensor device performance.