An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

In some examples, an electronic device comprises a voltage supply circuit to provide a reference voltage usable to discharge pixels in a display device; and a scaler circuit coupled to the voltage supply circuit. The scaler circuit is to buffer first and second frames and dynamically control the voltage supply circuit to modify the reference voltage based on a frequency of the first frame differing from a frequency of the second frame.

In some examples, an electronic device comprises a voltage supply circuit to provide a reference voltage usable to discharge pixels in a display device; and a scaler circuit coupled to the voltage supply circuit. The scaler circuit is to buffer first and second frames and dynamically control the voltage supply circuit to modify the reference voltage based on a frequency of the first frame differing from a frequency of the second frame.

A voltage generation circuit includes an operation voltage driving circuit configured to drive an operation voltage based on a calibration voltage and a feedback voltage and generate the feedback voltage from the operation voltage. The voltage generation circuit also includes a reference voltage calibration circuit configured to generate the calibration reference voltage, wherein the calibration reference voltage varies based on a set value calculated according to the feedback voltage and a reference voltage.

A voltage generation circuit includes an operation voltage driving circuit configured to drive an operation voltage based on a calibration voltage and a feedback voltage and generate the feedback voltage from the operation voltage. The voltage generation circuit also includes a reference voltage calibration circuit configured to generate the calibration reference voltage, wherein the calibration reference voltage varies based on a set value calculated according to the feedback voltage and a reference voltage.

Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and a second AND gate with a first input and a second input connected to the inverse output of the first latch, wherein the first input is configured to receive a second power on reset signal based upon the second power source line, wherein the mode of the circuit is indicated by the outputs of the first latch and the second latch.

Provided is a reference voltage circuit including a first MOS transistor to a sixth MOS transistor, a first resistor and a second resistor, a current source circuit, and an output terminal. Five of the transistors form a differential transconductance amplifier, and an input transistor of the differential transconductance amplifier operates in the manner of weak inversion operation.

A voltage generation circuit includes an operation voltage driving circuit configured to drive an operation voltage based on a calibration voltage and a feedback voltage and generate the feedback voltage from the operation voltage. The voltage generation circuit also includes a reference voltage calibration circuit configured to generate the calibration reference voltage, wherein the calibration reference voltage varies based on a set value calculated according to the feedback voltage and a reference voltage.

A voltage generation circuit includes an operation voltage driving circuit configured to drive an operation voltage based on a calibration voltage and a feedback voltage and generate the feedback voltage from the operation voltage. The voltage generation circuit also includes a reference voltage calibration circuit configured to generate the calibration reference voltage, wherein the calibration reference voltage varies based on a set value calculated according to the feedback voltage and a reference voltage.