Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

A power converter with an isolated topology may include a power transistor, a sense transistor, and a read-out circuit. The sense transistor may be arranged in a current mirror configuration with the power transistor such that the gate terminal of the sense transistor is coupled to the gate terminal of the power transistor and the first drain/source terminal of the sense transistor is coupled to the first drain/source terminal of the power transistor. The read-out circuit may be coupled to the second drain/source terminal of the power transistor and the second drain source/terminal of the sense transistor. The read-out circuit may be arranged to cause a voltage at the second drain/source terminal of the sense transistor to be substantially the same as a voltage at the second drain/source terminal of the power transistor.

A power converter with an isolated topology may include a power transistor, a sense transistor, and a read-out circuit. The sense transistor may be arranged in a current mirror configuration with the power transistor such that the gate terminal of the sense transistor is coupled to the gate terminal of the power transistor and the first drain/source terminal of the sense transistor is coupled to the first drain/source terminal of the power transistor. The read-out circuit may be coupled to the second drain/source terminal of the power transistor and the second drain source/terminal of the sense transistor. The read-out circuit may be arranged to cause a voltage at the second drain/source terminal of the sense transistor to be substantially the same as a voltage at the second drain/source terminal of the power transistor.

A semiconductor device includes: a voltage generation unit that generates a first voltage having a first temperature characteristic; a constant voltage generation unit that generates a constant voltage; and an adjustment unit that generates a second voltage having a second temperature characteristic and a third voltage having a third temperature characteristic using the first voltage and the constant voltage. The constant voltage generation unit generates the constant voltage independently of the adjustment unit. One of the second and third temperature characteristics is an opposite characteristic to the first temperature characteristic. The device can also include a control unit that selects one of the second and third voltages in response to a predetermined setting value.

A semiconductor device includes: a voltage generation unit that generates a first voltage having a first temperature characteristic; a constant voltage generation unit that generates a constant voltage; and an adjustment unit that generates a second voltage having a second temperature characteristic and a third voltage having a third temperature characteristic using the first voltage and the constant voltage. The constant voltage generation unit generates the constant voltage independently of the adjustment unit. One of the second and third temperature characteristics is an opposite characteristic to the first temperature characteristic. The device can also include a control unit that selects one of the second and third voltages in response to a predetermined setting value.

An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

A Proportional-To-Absolute-Temperature (PTAT) current source is used for high-resolution temperature measurement. The PTAT current source is coupled to a capacitor for a fixed amount of time so as to charge the capacitor to a voltage which is proportional to the current applied to the capacitor, and thus proportional to the temperature. The voltage on the capacitor is measured, and a temperature is calculated or determined from the measured voltage.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.