A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.

A modular system is described which can provide high frequency monitoring of power use and responsive control as well as enabling network connectivity for centralised monitoring and operation. One modular system consists of a communications bus, end caps, and a combination of the modules providing communications, power metering, relay control and battery backup. Each modular system can be configured with a combination of modular units as needed for the application. A combination of bus communication monitoring and tilt detection provides security against external tampering after installation.

Methods, systems, and computer readable media for smart network interface card testing are disclosed. One example method occurs at a network interface card (NIC) comprising a network processing unit executing a monitoring agent for monitoring data traversing the NIC. The method includes obtaining, from a test system or a test traffic generator, at least one test packet; generating, using the monitoring agent, NIC processing information associated with processing the at least one test packet, wherein generating the NIC processing information includes monitoring application layer events, presentation layer events, session layer events, transport layer events, network layer events, driver layer events, kernel layer events, or other events involving the NIC and generating the NIC processing information using the monitored events; and storing or providing the NIC processing information for data analysis.

It is provided an information processing apparatus. The information processing apparatus includes memory, a processor configured to control a device, a circuit connected with the memory, the processor and the device and configured to store a first sequence which causes a failure of the device in a first storage area in the memory, store a second sequence which prevents the failure in a second storage area in the memory, determine whether a third sequence for controlling the device included in a packet output from the processor is the first sequence, coordinate the third sequence by using the second sequence when the third sequence is the first sequence, and generate a packet including the coordinated third sequence.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

A vehicle includes a data communication network, a serial data bus, and a plurality of electronic nodes in signal communication with the serial data bus. The vehicle further includes a node identification system configured to store a several different diagnostic tests, along with expected operating data corresponding to a given diagnostic test. The node identification system sorts the plurality of nodes into individual node groups in response to performing one or more diagnostic tests among the different available diagnostic tests.

To locate an intermittent fault in a communication structure of an aircraft comprising pieces of equipment that are interconnected by cabling forming a plurality of communication media that are shared, an analyzer retrieves an error report relating to transmission errors observed on each of said communication media, performs a count of the transmission errors, per type of error and per communication chain, computes a median of the counts for communication chains comprising the same pair of wired pieces of equipment, and when, for a communication chain, the count exceeds a threshold equal to the median plus a predefined margin, generates an alarm indicating detection of an intermittent fault in association with the communication chain that led the threshold to be exceeded. Thus, intermittent faults are easily located and repaired.

The invention relates to a method for diagnosing a fieldbus type network. The method comprises the steps of measuring, using a signal measuring device such as an oscilloscope, a bus signal of the fieldbus type network, providing the measured bus signal to a computer system, and generating, by the computer system, a diagnosis. The diagnosis is performed by executing a step of comparing, by the computer system, the measured bus signal with signals in a database of bus signals and corresponding diagnoses; and/or feeding, by the computer system, the measured bus signal to a trained statistical model trained to diagnose the fieldbus type network; as well as a step of outputting the diagnosis based on the output of the comparison and/or the output of the statistical model.

A testing device including a main housing, and a probe housing, wherein the probe housing is rotatably coupled to the main housing. The testing device further includes a first test probe and a second test probe. The first test probe may be configured to be inserted into an alternating-current receptacle. The second test probe is coupled to the probe housing. The second test probe may be configured to be inserted into a universal serial bus receptacle.

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.