Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

Memory access control circuitry controls handling of a memory access request based on at least one memory access control attribute associated with a region of address space including the target address. The memory access control circuitry comprises: lookup circuitry comprising a plurality of sets of comparison circuitry, each set of comparison circuitry to detect, based on at least one address-region-indicating parameter associated with a corresponding region of address space, whether the target address is within the corresponding region of address space; region mismatch prediction circuitry to provide a region mismatch prediction indicative of which of the sets of comparison circuitry is predicted to detect a region mismatch condition; and comparison disabling circuitry to disable at least one of the sets of comparison circuitry that is predicted by the region mismatch prediction circuitry to detect the region mismatch condition for the target address.

Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor.

To realize a low power consumption and a small area of a network communication system and a semiconductor device for mounting the same. In the processing method of the network router or network communication frame, the received frame is input to the hash generator, to obtain an address based on the resulting hash value, the position of the address in the rule table, stores the rule corresponding to the received frame.

A master request comprising a plurality of bits is received, each bit representing whether a host device of a plurality of host devices has issued a memory access request. The master request is divided into a plurality of slices, each respective slice containing a subset of the plurality of bits corresponding a subset of host devices. Based on the respective subsets of the plurality of bits, it is determined whether each respective slice contains at least one memory access request. A first round robin process then begins in which it is determined whether each respective slice contains a memory access request. If so, any memory access request contained in the respective slice are processed via a second round robin process before proceeding to process memory access requests of another slice. If the respective slice contains no memory access requests, processing skips to a next slice without processing the respective slice.

A memory controller configured to control a dynamic random access memory (DRAM) includes a first control circuit and a second control circuit. The first control circuit is configured to store a request received by the memory controller in a first storage circuit, and select a request from all requests stored in the first storage circuit. The second control circuit is configured to store the request selected by the first control circuit in a second storage circuit, reorder requests stored in the second storage circuit, generate a DRAM command, and issue the DRAM command to the DRAM. The first control circuit is configured to select the request based on target banks and target pages of the requests stored in the second storage circuit, and a state of a bank or page of the DRAM.

An information processing device include: a memory; and a processor coupled to the memory and configured to: receive an access request directed to an access target and sets the access request in any one of a plurality of pending entries each of which includes latency information; issue a command that corresponds to the access request; control issuance of the command on a basis of the latency information of the any one of the pending entries; set a value that indicates latency for the access request in the latency information of the any one of the pending entries; and subtract a predetermined value from the latency information of the any one of the pending entries for each unit of time.

A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.

A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.