A semiconductor memory module for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, the memory module for shared memory access includes a memory cube providing high capacity memory coupled to multiple multi-port memories to support simultaneous memory access at multiple memory interfaces. In other embodiments, a memory module incorporates a processor to implement computational memory architecture. In some embodiments, a mini core memory system implements a memory architecture for providing direct and parallel memory access to a mini processor core array.

A computing storage architecture is disclosed. Memory devices may incorporate distributed processors and memory. The devices can be arranged using multiple packages, each package including one, or multiple, dies. In one aspect of the disclosure, any of the processors on a first die may transfer data to and from any processor on a second die internally within the device without having to pass through an external storage controller. In another aspect of the disclosure, a multi-package processing architecture allows for both in-package and inter-channel data transfers between processors within the same device. In still another aspect of the disclosure, one or more processors may include a preemptive scheduler circuit, which enables a processor to interrupt an ongoing lower priority transmission and to immediately transfer data.

A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.

A memory module adapter card can adapt multiple compression-attached memory modules (CAMMs) to a dual inline memory module (DIMM) connector. Multiplexer circuitry on the adapter card enables multiplexing data amongst the memory modules attached to the adapter card during a same burst access sequence.

A system enables entities to access a single platform in order to utilize electronic data storage for storing different types of information. One or more computers may operate an electronic data storage processing network that entities can access when updating information in electronic data storage. The electronic data storage processing network may operate a plurality of electronic data storage processing modules, which can include an aggregator module, a formatter module, an operator signer module, and a validator module. Based on the specific use case for which electronic data storage is utilized, recordable data that is to be added to the electronic data storage can be processed by the appropriate aggregating, formatting, signing, and validating functions provided by the electronic data storage processing modules.

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

A memory device includes a first chip and a second chip. The first chip includes a first storage array and a second storage array. The first storage array includes at least one first storage block. The first storage block includes a plurality of first word lines extending in a first direction and a plurality of first bit lines extending in a second direction. The second storage array includes at least one second storage block. By constructing a first global bit line sub-decoder block in a first overhead projection area formed by the first storage block and constructing a second global bit line sub-decoder block in a second overhead projection area formed by the second storage block, an occupied area of the first chip and the second chip after stacking can be reduced, which reduces an occupied area of the memory device and is beneficial for minimizing the memory device.

A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.

Semiconductor memory systems and architectures for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, a memory processor array includes an array of memory cubes, each memory cube in communication with a processor mini core to form a computational memory. In another embodiment, a memory system includes processing units and one or more mini core-memory module both in communication with a memory management unit. Mini processor cores in each mini core-memory module execute tasks designated to the mini core-memory module by a given processing unit using data stored in the associated quasi-volatile memory circuits of the mini core-memory module.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling, by an on-chip memory controller, a plurality of hardware components that are configured to perform computations to access a shared memory. One of the on-chip memory controller includes at least one backside arbitration controller communicatively coupled with a memory bank group and a first hardware component, wherein the at least one backside arbitration controller is configured to perform bus arbitrations to determine whether the first hardware component can access the memory bank group using a first memory access protocol; and a frontside arbitration controller communicatively coupled with the memory bank group and a second hardware component, wherein the frontside arbitration controller is configured to perform bus arbitrations to determine whether the second hardware component can access the memory bank group using a second memory access protocol different from the first memory access protocol.