Patent classifications
G06F13/1657
Storage backed memory package save trigger
Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.
AN APPARATUS AND METHOD FOR HANDLING MEMORY ACCESS REQUESTS
A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.
TRANSFER DEVICE, TRANSFER METHOD, AND TRANSFER PROGRAM
A transfer device is a transfer device that distributes and transfers a plurality of pieces of data to a plurality of information processing devices that perform control to record data on a magnetic tape, in which the transfer device transfers data to the plurality of information processing devices such that the number of pieces of data is leveled between the plurality of information processing devices, and transfers a plurality of pieces of data of which a value indicating a probability that a plurality of pieces of data are read within a predetermined period is a threshold value or greater, to the same information processing device.
Lookahead priority collection to support priority elevation
A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.
High bandwidth memory system with distributed request broadcasting masters
A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.
Arrangements for storing more data in memory
Data employed in computations is processed so that during computations more of the data can be fit into or maintained in a smaller but higher speed memory than an original source of the data. More specifically, a sensitivity value is determined for various items of the data which reflect the number of bits in the data items that are not garbage bits, and only information in the data items that are indicated by the sensitivity value to not be garbage bits are necessarily effectively retained. At least the information that is not garbage bits and the corresponding associated sensitivity are packed together. The results of computations that are performed using the data items as at least one of the operands for the computation are associated with a sensitivity that is derived from the individual sensitivities of the operands used in the computation.
High bandwidth memory system with crossbar switch for dynamically programmable distribution scheme
A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.
Isolation of protective functions in electrical power systems
Systems, devices, and methods include protective functions in an electrical power system. For example, a processing subsystem may include a first processor and a second processor. The first processor and the second processor may operate independently. A memory subsystem may comprise a first memory section and a second memory section. A memory management subsystem may enable memory access between the first processor and the first memory section and disable memory access between the first processor and the second memory section. The memory management subsystem may further enable memory access between the second processor and the second memory section and disable memory access between the second processor and the first memory section. A protection subsystem may include the first processor and the first memory section and enable a protection function. The second processor and the second memory section may provide a second function that operates independently of the protection function.
Modular data processing and storage system
A system enables entities to access a single platform in order to utilize electronic data storage for storing different types of information. One or more computers may operate an electronic data storage processing network that entities can access when updating information in electronic data storage. The electronic data storage processing network may operate a plurality of electronic data storage processing modules, which can include an aggregator module, a formatter module, an operator signer module, and a validator module. Based on the specific use case for which electronic data storage is utilized, recordable data that is to be added to the electronic data storage can be processed by the appropriate aggregating, formatting, signing, and validating functions provided by the electronic data storage processing modules.
Data processing on memory controller
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.