A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

A computing system for supporting a plurality of different types of memory devices includes a memory voltage regulator. The memory voltage regulator adjusts a supply voltage to a requisite voltage for a detected memory device based on serial presence detect (SPD) data. The computing system further includes a memory controller that supports a plurality of types of memory devices. The memory controller receives data regarding the type of the detected memory device, and controls input/output signals relative to the type of the detected memory device based on the SPD data and the GPIO data of the detected memory device.

Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

The present disclosure discloses a control device of data storage system, including a host interface, a peer interface, a storage unit interface, a processor and a local data management module. The host interface is connected and communicated with a storage server for data interaction with the storage server. The peer interface is configured for data communication connection with a storage unit of an adjacent control device in the data storage system. The storage unit interface is configured to connect a storage unit. The local data management module is configured for local data management of the data in the storage unit according to the data management instruction via the processor. The host interface is configured to send result data of local data management to the storage server.

Methods, systems, and devices for initializing memory systems are described. A memory system may transmit, to a host system over a first channel, signaling indicative of a first set of values for a set of parameters associated with communicating information over a second channel between a storage device of the memory system and a memory device of the memory system. The host system may transmit, to the memory system, additional signaling associated with the first set of values for the set of parameters. For instance, the host system may transmit a second set of values for the set of parameters, an acknowledgement to use the first set of values, or a command to perform a training operation on the second channel to identify a second set of values for the set of parameters. The memory system may communicate the information over the second channel based on the additional signaling.

This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

A method is for operating a nonvolatile dual in-line memory module (NVDIMM). The NVDIMM includes a dynamic random access memory (DRAM) and a nonvolatile memory (NVM) device, the DRAM including a first input/output (I/O) port and a second I/O port, and the second I/O port connected to the NVM device. The method includes receiving an externally supplied command signal denoting a read/write command and a transfer mode, driving a multiplexer to select at least one of the first and second I/O ports according to the transfer mode of the command signal, and reading or writing data according to the read/write command of the command signal in at least one of the DRAM and NVM device using the at least one of the first and second I/O ports selected by driving the multiplexer.