A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

A first electronic device for communication with a second electronic device on a single wire interface, includes: a memory; and a processor executing an application stored in the memory. The processor is configured to: receive, from the second electronic device, interrupt signals related with a frequency and a time space, over the single wire interface; decode an input data associated with the interrupt signals based on an interrupt protocol table; and provide the decoded input data to the application on the first electronic device.

A first electronic device for communication with a second electronic device on a single wire interface, includes: a memory; and a processor executing an application stored in the memory. The processor is configured to: receive, from the second electronic device, interrupt signals related with a frequency and a time space, over the single wire interface; decode an input data associated with the interrupt signals based on an interrupt protocol table; and provide the decoded input data to the application on the first electronic device.

A method for searching for an interrupted device, a slave device, a master device, and a storage medium. The method includes: connecting slave devices to a master device through a connection device; receiving, by the slave devices, task process information sent by the master device, where the task process information includes: task process information recorded by the master device and the corresponding slave devices when executing tasks; and when the receiving of task process information sent by the master device is interrupted, finding an interrupted slave device according to the interrupted task process information.

A method for searching for an interrupted device, a slave device, a master device, and a storage medium. The method includes: connecting slave devices to a master device through a connection device; receiving, by the slave devices, task process information sent by the master device, where the task process information includes: task process information recorded by the master device and the corresponding slave devices when executing tasks; and when the receiving of task process information sent by the master device is interrupted, finding an interrupted slave device according to the interrupted task process information.

Methods, apparatus, systems, and articles of manufacture are disclosed to manage processor interrupts. An example apparatus includes at least one memory; instructions; and processor circuitry. The processor circuitry is to execute the instructions to receive an interrupt for a direct memory access to transfer a packet. The processor circuitry is to execute the instructions to decode a priority field in the packet to associate the interrupt with a traffic class. The processor circuitry is to execute the instructions to route the interrupt to an interrupt timer based on the traffic class, the interrupt timer to mask interrupts transmitted to the interrupt timer for a threshold period after receiving the interrupt. The processor circuitry is to execute the instructions to send the interrupt after the threshold period.

Methods, apparatus, systems, and articles of manufacture are disclosed to manage processor interrupts. An example apparatus includes at least one memory; instructions; and processor circuitry. The processor circuitry is to execute the instructions to receive an interrupt for a direct memory access to transfer a packet. The processor circuitry is to execute the instructions to decode a priority field in the packet to associate the interrupt with a traffic class. The processor circuitry is to execute the instructions to route the interrupt to an interrupt timer based on the traffic class, the interrupt timer to mask interrupts transmitted to the interrupt timer for a threshold period after receiving the interrupt. The processor circuitry is to execute the instructions to send the interrupt after the threshold period.

The present invention relates to a semiconductor device having a first processor element configured to receive a first interrupt request signal, a second processor element configured to receive a second interrupt request signal, a first priority determination circuit configured to receive a plurality of interrupt signals and to output the first interrupt request signal to the first processor element, a second priority determination circuit configured to receive the plurality of interrupt signals and to output the second interrupt request signal to the second processor element, a checker circuit configured detect failures of the first priority determination circuit and the second priority determination circuit, and a control circuit configured to select one of the first priority determination circuit or the second priority determination circuit as a circuit to be checked. The control circuit selects the circuit to be checked based on the first interrupt request signal and the second interrupt request signal.

The present invention relates to a semiconductor device having a first processor element configured to receive a first interrupt request signal, a second processor element configured to receive a second interrupt request signal, a first priority determination circuit configured to receive a plurality of interrupt signals and to output the first interrupt request signal to the first processor element, a second priority determination circuit configured to receive the plurality of interrupt signals and to output the second interrupt request signal to the second processor element, a checker circuit configured detect failures of the first priority determination circuit and the second priority determination circuit, and a control circuit configured to select one of the first priority determination circuit or the second priority determination circuit as a circuit to be checked. The control circuit selects the circuit to be checked based on the first interrupt request signal and the second interrupt request signal.

The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.