A method includes exposing a public cryptographic key associated with a peripheral device of a computing system to a guest running on the computing system. The method further includes receiving, from the guest, a message including a cryptographic nonce value encrypted with the public cryptographic key. The method further includes producing the cryptographic nonce value by decrypting the message using a private cryptographic key associated with the public cryptographic key. The method further includes using a shared cryptographic key generated from the cryptographic nonce value to access contents of a direct memory access (DMA) buffer associated with the peripheral device.

A method includes exposing a public cryptographic key associated with a peripheral device of a computing system to a guest running on the computing system. The method further includes receiving, from the guest, a message including a cryptographic nonce value encrypted with the public cryptographic key. The method further includes producing the cryptographic nonce value by decrypting the message using a private cryptographic key associated with the public cryptographic key. The method further includes using a shared cryptographic key generated from the cryptographic nonce value to access contents of a direct memory access (DMA) buffer associated with the peripheral device.

A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.

A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.

Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

A motor driver, a control method of the motor driver, and a motor driving system are provided. The motor driver includes a rotation information pin, an analog detecting circuit and a mode switching circuit. The rotation information pin is configured to receive a reference signal. The analog detecting circuit and the mode switching circuit are respectively and electrically connected to the rotation information pin and the analog detecting circuit. The analog detecting circuit determines whether the reference signal is an analog signal, and the motor driver is maintained in a master mode when the reference signal does not belong to the analog signal. The mode switching circuit determines whether the reference signal is a noise when the reference signal is the analog signal. The mode switching circuit switches the motor driver from the master mode to a slave mode when the reference signal is not the noise.

A motor driver, a control method of the motor driver, and a motor driving system are provided. The motor driver includes a rotation information pin, an analog detecting circuit and a mode switching circuit. The rotation information pin is configured to receive a reference signal. The analog detecting circuit and the mode switching circuit are respectively and electrically connected to the rotation information pin and the analog detecting circuit. The analog detecting circuit determines whether the reference signal is an analog signal, and the motor driver is maintained in a master mode when the reference signal does not belong to the analog signal. The mode switching circuit determines whether the reference signal is a noise when the reference signal is the analog signal. The mode switching circuit switches the motor driver from the master mode to a slave mode when the reference signal is not the noise.

Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.