Throttling recommendations for a systolic array may be arbitrated. Throttling recommendations may be received at an arbiter for a systolic array from different sources, such as one or more monitors implemented in an integrated circuit along with the systolic array or sources external to the integrated circuit with the systolic array. A strongest throttling recommendation may be selected. The rate at which data enters the systolic array may be modified according to the strongest throttling recommendation.

Throttling recommendations for a systolic array may be arbitrated. Throttling recommendations may be received at an arbiter for a systolic array from different sources, such as one or more monitors implemented in an integrated circuit along with the systolic array or sources external to the integrated circuit with the systolic array. A strongest throttling recommendation may be selected. The rate at which data enters the systolic array may be modified according to the strongest throttling recommendation.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

A control method for a first device of an inter-integrated circuit (I.sup.2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I.sup.2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I.sup.2C system when determining that the status information of the first device matches the target status.

A control method for a first device of an inter-integrated circuit (I.sup.2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I.sup.2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I.sup.2C system when determining that the status information of the first device matches the target status.

The present disclosure provides an access arbitration system and method for a plurality of I2C communication-based master devices. The system includes: a slave device; a plurality of master devices, respectively connected to the slave device through I2C buses; and an arbitration logic controller, respectively connected to the plurality of master devices. When the master devices need to access the slave device, the master devices send access requests for an I2C bus access permission to the arbitration logic controller, the arbitration logic controller determines, based on the access requests of the master devices, the master device that establishes a communication connection with the slave device, and sends a connection confirmation instruction to the corresponding master device, and the master device that receives the connection confirmation instruction establishes the communication connection with the slave device. In the present disclosure, the reliability of system operation is improved.

The present disclosure provides an access arbitration system and method for a plurality of I2C communication-based master devices. The system includes: a slave device; a plurality of master devices, respectively connected to the slave device through I2C buses; and an arbitration logic controller, respectively connected to the plurality of master devices. When the master devices need to access the slave device, the master devices send access requests for an I2C bus access permission to the arbitration logic controller, the arbitration logic controller determines, based on the access requests of the master devices, the master device that establishes a communication connection with the slave device, and sends a connection confirmation instruction to the corresponding master device, and the master device that receives the connection confirmation instruction establishes the communication connection with the slave device. In the present disclosure, the reliability of system operation is improved.

In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.