A data transmission method and a data transmission apparatus are provided. The data transmission method, performed by the data transmission apparatus, wherein the data transmission apparatus includes a first communication unit and a second communication unit, both the first communication unit and the second communication unit transmit data using a first communication protocol, wherein the method includes: the first communication unit acquiring media data from an electronic apparatus; the first communication unit sending the media data to the second communication unit using the first communication protocol; and the second communication unit receiving the media data, and sending the media data to an interactive white board using the first communication protocol.

A data network has at least three line branches connected via a common star node to distribute message signals from one of the line branches onto the other line branches, wherein connected to at least one of the line branches is at least one bus-user device is configured to generate in a corresponding transmit mode by a corresponding transmit unit at least one of the message signals, wherein in the corresponding bus-user device, the transmit unit has a current source circuit which, in generating the message signal (16), is configured to inject an electric current into electrical lines of the line branch to which the bus-user device is connected, and via the current source circuit the lines are connected to an internal impedance value of the current source circuit that in transmit mode is constantly greater than 10 times the value of the characteristic impedance, for example greater than 500 Ohms.

A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

Within an interrupt routing structure, an interrupt handler is registered, the registering comprising storing a pointer to the interrupt handler in the interrupt routing structure. Responsive to determining that a received interrupt comprises a queuing bypass flag in a set state, the interrupt handler is executed, the executing bypassing an interrupt queueing mechanism.

A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.

A device includes a plurality of reconfigurable resources, a bus, and a configurator. The bus interconnects the plurality of reconfigurable resources. The configurator is configured to deterministically compute a segmented interconnect configuration for the bus based on operational parameters associated with the device and operational constraints associated with program modules to be executed by the plurality of reconfigurable resources.

A method includes determining, by one or more processing entities associated with at least one of: one or more low voltage drive circuits (LVDCs) and one or more other LVDCs, an initial data conveyance scheme and an initial communication scheme for each communication of a plurality of communications on one or more lines of a bus. The method further includes determining a desired number of channels for each communication of the plurality of communications based on the initial data conveyance scheme and the initial communication scheme, a desired total number of channels for the plurality of communications based on the desired number of channels, determining whether the desired total number of channels for the plurality of communications exceeds a total number of available channels. If not, allocating the desired number of channels to each communication of the plurality of communications in accordance with the channel allocation mapping.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. In a representative embodiment, a system includes an interconnection network, a processor, a host interface, and a configurable circuit cluster. The configurable circuit cluster may include a plurality of configurable circuits arranged in an array; an asynchronous packet network and a synchronous network coupled to each configurable circuit of the array; and a memory interface circuit and a dispatch interface circuit coupled to the asynchronous packet network and to the interconnection network. Each configurable circuit includes instruction or configuration memories for selection of a current data path configuration, a master synchronous network input, and a data path configuration for a next configurable circuit.

A method for filtering communication data arriving from a communication partner via a communication connection, which provides access to at least one storage means of a receiving data processing device having at least one computation unit, in the data processing device, wherein PCI Express, in an interface unit, receiving the communication data, of the data processing device, a filter means, at least part of which is embodied as hardware, is used so that, according to configuration information, prescribed on the data processing device, containing at least one approval condition that rates the at least one property of the useful data contained in the communication data, only the communication data meeting at least one approval condition are forwarded from the interface unit to at least one further component of the data processing device.

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.