A processing system comprises a control bus and a plurality of logic units. The control bus is configurable by configuration data to form signal routes in a control barrier network coupled to processing units in an array of processing units. The plurality of logic units has inputs and outputs connected to the control bus and to the array of processing units. A logic unit in the plurality of logic units is operatively coupled to a processing unit in the array of processing units and is configurable by the configuration data to consume source tokens and a status signal from the processing unit on the inputs and to produce barrier tokens and an enable signal on the outputs based on the source tokens and the status signal on the inputs.

The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Disclosed is a task allocation method, apparatus, electronic device, and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, determining, by the microprocessor, whether allocation of a task segment to the processing core is required according to the synchronization signal, wherein the task segment is a part of a task; in response to the allocation of the task segment to the processing core being required, instructing, by the microprocessor, to allocate the task segment to the processing core; receiving, by the processing core, the task segment; and in response to satisfying a first preset condition, sending, by the processing core, a synchronization request signal, wherein the synchronization request signal is configured to trigger the generation of the synchronization signal.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

A set of configurable sync groupings (which may be referred to as sync zones) are defined. Any of the processors may belong to any of the sync zones. Each of the processor comprises a register indicating to which of the sync zones it belongs. If a processor does not belong to a sync zone, it continually asserts a sync request for that sync zone to the sync controller. If a processor does belong to a sync zone, it will only assert its sync request for that sync zone upon arriving at a synchronisation point for that sync zone indicated in its compiled code set.

Disclosed examples include an apparatus. The apparatus may include first interfaces, second interfaces, a bus interface, and a buffer interface. The first interfaces may be to communicate at first data widths via first interconnects for operable coupling with data samples sources. The second interface may be to communicate at second data widths via second interconnects for operable coupling with data sinks. The buffer interface may be to communicate with a system to process data samples sampled using different sampling rates according to processing frame durations. The buffer interface may include an uplink channel handler and a downlink channel handler. The uplink channel handler may be to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths. The downlink channel handler may be to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths. The bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory region utilized by the system to process data samples.

A method comprises collecting message-oriented-middleware system parameters from a plurality of message-oriented-middleware clusters, analyzing the parameters using one or more machine learning algorithms, and predicting, based at least in part on the analyzing, at least one anomaly in a message-oriented-middleware cluster of the plurality of message-oriented-middleware clusters. In the method, message metadata is collected from the message-oriented-middleware cluster, and at least part of the message metadata is transmitted to one or more remaining ones of the plurality of message-oriented-middleware clusters. At least the part of the message metadata corresponds to messaging operations to be transferred from the message-oriented-middleware cluster to the one or more remaining ones of the plurality of message-oriented-middleware clusters.

In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

A control system for factory automation includes a first unit and a second unit each including a timer, a data line over which data containing a timer value indicated by the timer is exchanged between the first unit and the second unit, a signal line that electrically connects the first unit and the second unit, and an adjustment module connected to the signal line and the data line. The adjustment module acquires, when receiving a trigger signal over the signal line, the timer value over the data line and matches the timer of the second unit with the timer of the first unit based on the timer value acquired.

A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.