A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

A system to synchronize application data bidirectionally between N clients and one server, by: (a) pushing mutations made in the client to the server, wherein each mutation is comprised of a mutation name identifying the type of mutation, and arguments provided by the application modifying the behavior of the mutation, and the pusher also pushes a client ID and mutation ID for each mutation to the server; (b) pulling server differentials to the client; (c) storing key/value pairs in a versioned cache, wherein the keys are text strings and the values are data provided by an application in the client; and (d) resolving conflicts between the client and the server with a rebaser that: forks the cache to create a synch branch when the client receives the latest server differential, applies the latest received server differential to the synch branch, applies only those mutations to the synch branch that have not already been acknowledged by the server, and then makes the synch branch the main branch of the cache.

A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Described is an improved approach to implement fast detection of node death. Instead of just relying on multiple heart beats to fail in order to determine whether a node is dead, the present approach performs an on demand validation using RDMA to determine whether the node is reachable, where the approach of using RDMA is significantly faster than the heartbeat approach.

Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.

Described are methods, systems and computer readable media for dynamic updating of query result displays.

A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.

Described are methods, systems and computer readable media for performance logging of complex query operations.

Techniques are described for offloading remote direct memory operations (RDMOs) to “execution candidates”. The execution candidates may be any hardware capable of performing the offloaded operation. Thus, the execution candidates may be network interface controllers, specialized co-processors, FPGAs, etc. The execution candidates may be on a machine that is remote from the processor that is offloading the operation, or may be on the same machine as the processor that is offloading the operation. Details for certain specific RDMOs, which are particularly useful in online transaction processing (OLTP) and hybrid transactional/analytical (HTAP) workloads, are provided.