A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

A physical-layer circuit including a memory, a physical-layer device and a control circuit. The memory receives data from a media access controller (MAC) at a first rate. The MAC is separate from the physical-layer circuit. The physical-layer device receives the data from the memory and transmits the data from the physical-layer circuit to a peer device. The physical-layer device transfers the data from the memory to the peer device at a second rate. An amount of data stored in the memory is based on a difference between the first and second rates. The second rate is less than the first rate. The control circuit is connected between the memory and the physical layer device. The control circuit monitors the amount of the data stored in the memory and, based on the amount of the data stored in the memory, transmits a frame to the MAC to decrease the first rate.

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Disclosed herein is a data management system for storing a plurality of incoming data streams. The data management system utilizes a high speed storage device in combination with an intelligent FIFO process to reliably store the incoming data streams to a storage device without fragmentation. The data management system further includes one or more external storage devices that can be used for archival purposes.