Patent classifications
G06F2212/151
Emulated edge locations in cloud-based networks for testing and migrating virtualized resources
Various techniques for emulating edge locations in cloud-based networks are described. An example method includes generating an emulated edge location in a region. The emulated edge location can include one or more first computing resources in the region. A host in the region may launch a virtualized resource a portion of the one or more first computing resources. Output data that was output by the virtualized resource in response to input data can be received and reported to a user device, which may provide a request to migrate the virtualized resource to a non-emulated edge location. The non-emulated edge location may include one or more second computing resources that are connected to the region by an intermediary network. The virtualized resource can be migrated from the first computing resources to at least one second computing resource in the non-emulated edge location.
Maintenance command interfaces for a memory system
Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.
Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system
Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.
DATA LOCALITY IN A HYPERCONVERGED COMPUTING SYSTEM
Some examples describe data locality solutions for a hyperconverged computing system. In an example, a data request may be received at a Virtual Storage Appliance (VSA) node amongst a plurality of VSA nodes in a hyperconverged computing system. A determination may be made whether a remapped logical block address (LBA) associated with the data request is included on a first mapping layer on the VSA node. In response to a determination that the remapped LBA associated with the data request is present on the first mapping layer of the VSA node, the remapped LBA may be used to resolve the data request. In response to a determination that the remapped LBA associated with another data request is not present on the first mapping layer of the VSA node, a second mapping layer on the VSA node may be used to resolve the other data request.
RESTRICTED ADDRESS TRANSLATION TO PROTECT AGAINST DEVICE-TLB VULNERABILITIES
An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.
Reducing Translation Lookaside Buffer Searches for Splintered Pages
Systems, apparatuses, and methods for performing efficient translation lookaside buffer (TLB) invalidation operations for splintered pages are described. When a TLB receives an invalidation request for a specified translation context, and the invalidation request maps to an entry with a relatively large page size, the TLB does not know if there are multiple translation entries stored in the TLB for smaller splintered pages of the relatively large page. The TLB tracks whether or not splintered pages for each translation context have been installed. If a TLB invalidate (TLBI) request is received, and splintered pages have not been installed, no searches are needed for splintered pages. To refresh the sticky bits, whenever a full TLB search is performed, the TLB rescans for splintered pages for other translation contexts. If no splintered pages are found, the sticky bit can be cleared and the number of full TLBI searches is reduced.
Technology for moving data between virtual machines without copies
A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.
Systems and methods for transparent entering of a process into a virtual machine
Disclosed herein are systems and method for moving a process from a host to a virtual machine (VM). In one exemplary aspect, a method comprises freezing the process at a host operating system (OS) of the host; transferring at least one kernel object of the process from the host OS to a VM OS of the VM; reconfiguring at least one input-output (IO) resource of the process to point to a host-VM channel such that data flow between the host and the VM is enabled; mapping memory utilized by the process to the VM by remapping at least one page of the memory into the VM OS; and unfreezing the process at the VM OS.
PREPOPULATING PAGE TABLES FOR MEMORY OF WORKLOADS DURING LIVE MIGRATIONS
A method of populating page tables of an executing workload during migration of the executing workload from a source host to a destination host includes the steps of: before resuming the workload at the destination host, populating the page tables of the workload at the destination host, wherein the populating comprises inserting mappings from virtual addresses of the workload to physical addresses of system memory of the destination host; and upon completion of populating the page tables, resuming the workload at the destination host.
Optimization of data access and communication in memory systems
A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores the data items at the memory locations separated by different memory regions according to different contexts.