A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.

A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.

A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits. The local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.

Analysis of power supply noise in simulations of a design of a circuit can use per instance dynamic voltage drops (DVD) in timing analyses so that the simulated DVD values on a per victim cell basis can accurately guide the timing analysis on each victim instead of a global DVD for all victims during the timing analysis. In one embodiment, a method can: determine, during a power analysis simulation, a representation of an energy lost, during each switching window at each output of each victim cell, at one or more power supply rails of each of the victim cells in the set of victim cells due to aggressors in the design; and provide the representation of the energy lost separately for each victim cell to a timing analysis system. The representation can be a rectangle having a width defined by a switching window of a victim's output.

Analysis of power supply noise in simulations of a design of a circuit can use per instance dynamic voltage drops (DVD) in timing analyses so that the simulated DVD values on a per victim cell basis can accurately guide the timing analysis on each victim instead of a global DVD for all victims during the timing analysis. In one embodiment, a method can: determine, during a power analysis simulation, a representation of an energy lost, during each switching window at each output of each victim cell, at one or more power supply rails of each of the victim cells in the set of victim cells due to aggressors in the design; and provide the representation of the energy lost separately for each victim cell to a timing analysis system. The representation can be a rectangle having a width defined by a switching window of a victim's output.

This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.

A method of identifying, in a circuit design of an electronic circuit, a source of side channel leakage of the electronic circuit. The method comprises: a) simulating over a leakage time interval an operation of the circuit in response to at least one stimulus, thereby deriving for each one of the at least one stimulus per circuit part of the electronic circuit a respective simulated leakage quantity circuit part response over the leakage time interval; b) obtaining for each one of the at least one stimulus an expected leakage quantity response over the leakage time interval from a processing of each one of the at least one stimulus by a leakage model, the leakage model modelling a leak-quantity at a processing of a secure asset; c) determining respective circuit part correlations over the leakage time interval between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses; d) ranking the circuit parts based on the circuit part correlations between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses and e) identifying as the source of side channel leakage the circuit part for which a highest one of the circuit correlations has been determined between the expected leakage quantity responses and the respective simulated leakage quantity circuit part responses.

A method of identifying, in a circuit design of an electronic circuit, a source of side channel leakage of the electronic circuit. The method comprises: a) simulating over a leakage time interval an operation of the circuit in response to at least one stimulus, thereby deriving for each one of the at least one stimulus per circuit part of the electronic circuit a respective simulated leakage quantity circuit part response over the leakage time interval; b) obtaining for each one of the at least one stimulus an expected leakage quantity response over the leakage time interval from a processing of each one of the at least one stimulus by a leakage model, the leakage model modelling a leak-quantity at a processing of a secure asset; c) determining respective circuit part correlations over the leakage time interval between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses; d) ranking the circuit parts based on the circuit part correlations between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses and e) identifying as the source of side channel leakage the circuit part for which a highest one of the circuit correlations has been determined between the expected leakage quantity responses and the respective simulated leakage quantity circuit part responses.