A placement method for integrated circuit design is provided. Each net is considered as a soft module. The net will receive a larger penalty if it covers more routing congested regions. Therefore, it is easier to move the nets away from routing congested regions. In addition, to relieve local congestion, a novel inflation method is proposed to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. Accordingly, it can get better routability and wirelength.

A placement method for integrated circuit design is provided. Each net is considered as a soft module. The net will receive a larger penalty if it covers more routing congested regions. Therefore, it is easier to move the nets away from routing congested regions. In addition, to relieve local congestion, a novel inflation method is proposed to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. Accordingly, it can get better routability and wirelength.

An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.

A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.

Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Embodiments include thermally coupled aware device placement in the schematic design stage of the development of an integrated circuit. Aspects of the invention include obtaining a schematic design of a macro, the schematic design including a plurality of devices disposed within the macro. Aspects also include determining an initial temperature for each of the plurality of devices, where the initial temperature due to self-heating. Aspects further include determining, iteratively for each of the plurality of devices, an uplift temperature, where the uplift temperature for a first device of the plurality of devices is determined based on the initial temperature of each of the other plurality of devices and a distance between the first device and each of the other plurality of devices as encoded in the schematic design. Aspects also include modifying the schematic design of the macro based on a determination that the uplift temperature of at least one of the plurality of devices is above a threshold value.

Embodiments include thermally coupled aware device placement in the schematic design stage of the development of an integrated circuit. Aspects of the invention include obtaining a schematic design of a macro, the schematic design including a plurality of devices disposed within the macro. Aspects also include determining an initial temperature for each of the plurality of devices, where the initial temperature due to self-heating. Aspects further include determining, iteratively for each of the plurality of devices, an uplift temperature, where the uplift temperature for a first device of the plurality of devices is determined based on the initial temperature of each of the other plurality of devices and a distance between the first device and each of the other plurality of devices as encoded in the schematic design. Aspects also include modifying the schematic design of the macro based on a determination that the uplift temperature of at least one of the plurality of devices is above a threshold value.

Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.