A matrix processing method includes: determining a quantity of non-zero elements in a to-be-processed matrix, where the to-be-processed matrix is a one-dimensional matrix; generating a distribution matrix of the to-be-processed matrix, where the distribution matrix is used to indicate a position of a non-zero element in the to-be-processed matrix; combining the quantity of non-zero elements, values of all non-zero elements in the to-be-processed matrix arranged sequentially, and the distribution matrix, to obtain a compressed matrix of the to-be-processed matrix.

A matrix processing method includes: determining a quantity of non-zero elements in a to-be-processed matrix, where the to-be-processed matrix is a one-dimensional matrix; generating a distribution matrix of the to-be-processed matrix, where the distribution matrix is used to indicate a position of a non-zero element in the to-be-processed matrix; combining the quantity of non-zero elements, values of all non-zero elements in the to-be-processed matrix arranged sequentially, and the distribution matrix, to obtain a compressed matrix of the to-be-processed matrix.

A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.

A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.

A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.

A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.