Patent classifications
G06F7/4818
CORDIC COMPUTATION OF SIN/COS USING COMBINED APPROACH IN ASSOCIATIVE MEMORY
A method for an associative memory device includes the steps of providing a look up table (LUT) with all possible solutions for N first iterations of a CORDIC algorithm, receiving a plurality of input angles, concurrently computing a location index for each angle of the plurality of angles and concurrently storing each index in a column of the associative memory device, copying a solution from the LUT in the location index to a plurality of columns associated with the index and concurrently performing M additional iterations of the CORDIC algorithm on the columns to compute a value of a trigonometric function for each angle.
METHOD OF REALIZING ACCELERATED PARALLEL JACOBI COMPUTING FOR FPGA
The invention discloses a method of realizing accelerated parallel Jacobi computing for an FPGA. Data of a n×n-dimensional matrix are input to the FPGA, and a rotation transformation process is carried out by using parallel Jacobi computing. Processors are initialized. A diagonal processor computes a symbol set corresponding to a rotation angle and outputs the symbol set to a non-diagonal processor. Elements of the diagonal processor are updated. Elements of the non-diagonal processor are updated. Elements between the processors are exchanged. After the elements of the respective processors are updated, the updated elements between the processors are exchanged. The invention requires less FPGA resources while yields a higher internal computational processing performance of the FPGA. Accordingly, the invention is capable of facilitating the efficiency of realizing eigenvalue decomposition in the FPGA and is highly applicable in actual processing.
Structured-pipelined CORDIC for matrix equalization
Flexible structured-pipelined CORDIC techniques efficiently perform various CORDIC operations and support different parameters for MIMO MEQ processing. The structured-pipelined CORDIC techniques simplify signal processing flow, unify input requirements and output delay, and simplify integration. Look-up table techniques provide quick generation of control signals, reduce design and verification efforts, and facilitate design automation. In addition, the structured-pipelined CORDIC techniques are conducive to hardware sharing and reuse. The structured-pipelined CORDIC techniques reduce integrated circuit area and power consumption.
Hardware Algorithm for Complex-Valued Exponentiation and Logarithm Using Simplified Sub-Steps
A method of generating complex exponentiation and logarithms in hardware is described that uses half the number of bits of lookup tables as the state-of-the-art. By splitting up each of the iterations into more simplified stages or using more iterations, the amount of precomputed information that must be held by the circuitry is reduced. This allows synthesis tools to take this more succinct logical description of the algorithm and make it into efficient gate level logic for fabrication into more compact integrated circuitry.
STRUCTURED-PIPELINED CORDIC FOR MATRIX EQUALIZATION
Flexible structured-pipelined CORDIC techniques efficiently perform various CORDIC operations and support different parameters for MIMO MEQ processing. The structured-pipelined CORDIC techniques simplify signal processing flow, unify input requirements and output delay, and simplify integration. Look-up table techniques provide quick generation of control signals, reduce design and verification efforts, and facilitate design automation. In addition, the structured-pipelined CORDIC techniques are conducive to hardware sharing and reuse. The structured-pipelined CORDIC techniques reduce integrated circuit area and power consumption.
Method and system to enhance accuracy and resolution of system integrated scope using calibration data
This specification discloses methods and systems for implementing a chip integrated scope (i.e., chip scope (CS)), which is a feature that allows a user to scope RF signals (internally and externally to the DUT (device under test)), by using the RF receive path (including amplifier, filter, ADC, DSP) to capture and store signal traces. In some embodiments, this specification discloses methods and systems to enhance the resolution and accuracy of these signal traces by using raw and correction data for gain/phase compensation of gain/phase impairments introduced in the Rx (receiver) path. In some embodiments, the correction data is generated from one or more of the following: simulation data, characterization data, production test data.
METHOD AND SYSTEM TO ENHANCE ACCURACY AND RESOLUTION OF SYSTEM INTEGRATED SCOPE USING CALIBRATION DATA
This specification discloses methods and systems for implementing a chip integrated scope (i.e., chip scope (CS)), which is a feature that allows a user to scope RF signals (internally and externally to the DUT (device under test)), by using the RF receive path (including amplifier, filter, ADC, DSP) to capture and store signal traces. In some embodiments, this specification discloses methods and systems to enhance the resolution and accuracy of these signal traces by using raw and correction data for gain/phase compensation of gain/phase impairments introduced in the Rx (receiver) path. In some embodiments, the correction data is generated from one or more of the following: simulation data, characterization data, production test data
Digital circuitry and method for calculating inclinometer angles
A method is disclosed for performing calculations for an inclinometer device, as is a digital circuitry for performing such calculations. The circuitry comprises an interface for receiving detection signals from a sensor device and a CORDIC unit for performing calculation of inclinometer output values characterizing a resultant vector. The CORDIC calculation unit is configured to perform a calculation for resolving the angle between a resultant vector and a programmable reference value using hyperbolic CORDIC calculation. Pre-rotation may be performed for a vector before hyperbolic CORDIC arctangent calculation phases.
RF receiver with frequency tracking
A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing stage allows for a synchronization of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections, with a predetermined step.
Position error signal burst demodulation
A method may generate a demodulated sine component for a sequence of samples of a servo burst window of a position error signal using a sine weight look up table and generate a demodulated cosine component for the sequence of samples of the servo burst window of the position error signal using a cosine weight look up table. The sine weight and the cosine weight look up tables may have indexes representing a phase range. The method may generate a demodulated phase component signal and a demodulated amplitude component signal for the sequence of samples of the servo burst window of the position error signal based on the demodulated sine component and the demodulated cosine component using a Coordinate Rotation Digital Computer at least in part by iteratively rotating a vector based on the demodulated sine component and the demodulated cosine component and summing angular changes in the vector.