Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalized difference value.

An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalised difference value.

A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp+BexpCexp and determines the number of leading zeroes in C, if C is denormal. The microprocessor accumulates C with the partial products of A and B when the accumulation of C to the product of A and B could result in mass cancellation, when ExpDelta is greater than or equal to K (where K is related to a width of a datapath in the partial product adder), and when a C is denormal and its number of leading zeroes plus K exceeds ExpDelta. The strategic use of resources in the partial product adder and second accumulation stage reduces latency.

The disclosed herein related to a method for generating a partial stochastic rounding operation executed by a processor coupled to a memory. The method includes generating an intermediate result and causing a random number generator to generate a random number. The method also includes adding the random number to lower significant bits of the intermediate result to perturb any incrementing of most significant bits of the intermediate result to produce a resulting sum. The method also includes truncating the resulting sum into a final result. According to other embodiments, the above method can be implemented in a system or computer program product.

A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp+BexpCexp and determines the number of leading zeroes in C, if C is denormal. The microprocessor accumulates C with the partial products of A and B when the accumulation of C to the product of A and B could result in mass cancellation, when ExpDelta is greater than or equal to K (where K is related to a width of a datapath in the partial product adder), and when a C is denormal and its number of leading zeroes plus K exceeds ExpDelta. The strategic use of resources in the partial product adder and second accumulation stage reduces latency.

The disclosed herein related to a method for generating a partial stochastic rounding operation executed by a processor coupled to a memory. The method includes generating an intermediate result and causing a random number generator to generate a random number. The method also includes adding the random number to lower significant bits of the intermediate result to perturb any incrementing of most significant bits of the intermediate result to produce a resulting sum. The method also includes truncating the resulting sum into a final result. According to other embodiments, the above method can be implemented in a system or computer program product.

According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits. The rounding preprocessor performs an OR operation on lower (mk) bits of the first value to generate a second value of 1 bit. The register stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value. The rounding postprocessor calculates a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adds the carry bit value to upper n bits of the third value.