Disclosed is a method for designing an application task architecture for an electronic control unit based on an AUTOSAR operating system that is adaptable to a plurality of microcontrollers. Prior to association with a microcontroller, the method involves developing the application task architecture by using at least one virtual core different from the one or more cores of the microcontroller, the various tasks being assigned respectively to the at least one virtual core, and associating the at least one virtual core with the one or more cores of the microcontroller so as to allocate tasks assigned to the at least one virtual core to the core or among the cores of the microcontroller.

Systems, methods, and apparatuses relating to a scalable reservation station circuit implementing a single unified speculation state propagation and execution wakeup matrix in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode one or more instructions into a first micro-operation to load data from a data cache, a second micro-operation dependent on the first micro-operation, and a third micro-operation dependent on the second micro-operation; an execution circuit to execute the first micro-operation, the second micro-operation, and the third micro-operation; and a reservation station circuit comprising a load speculation tracker circuit and coupled between the decoder circuit and the execution circuit, the load speculation tracker circuit to, for a reservation station entry of the third micro-operation, track progress of the first micro-operation in the data cache to generate a cancellation indication for the third micro-operation in response to a miss of the data in the data cache for the first micro-operation, wherein the load speculation tracker circuit is to begin to track the progress of the first micro-operation in the data cache in response to a dispatch of the first micro-operation into the data cache.

A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

Provided herein may be a memory device which is capable of easily performing an update operation of a micro-code stored in the memory device. The memory device may include a first CAM block and a second CAM block, in which a micro-code is stored; and a control logic configured to control the first and second CAM blocks such that the stored micro-code is updated with a new micro-code in a micro-code update operation.

Disclosed is a method for designing an application task architecture for an electronic control unit based on an AUTOSAR operating system that is adaptable to a plurality of microcontrollers. Prior to association with a microcontroller, the method involves developing the application task architecture by using at least one virtual core different from the one or more cores of the microcontroller, the various tasks being assigned respectively to the at least one virtual core, and associating the at least one virtual core with the one or more cores of the microcontroller so as to allocate tasks assigned to the at least one virtual core to the core or among the cores of the microcontroller.

The memory device includes: a first CAM block and a second CAM block, in which a micro-code is stored; and a control logic configured to control the first and second CAM blocks such that the stored micro-code is updated with a new micro-code in a micro-code update operation.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

Described embodiments process data packets received by a switch coupled to a network processor. The switch determines whether one or more rules for classifying and processing the received packet are stored in an internal classification database of the switch. If one or more rules are stored in the internal database, the switch updates statistics corresponding to each of the rules and classifies and processes the received packet in accordance with the rules. If no associated rules are stored in the internal database, the switch tags the received packet with metadata and forwards the packet to the network processor. The network processor determines one or more rules for classifying and processing the forwarded packet in a classification database of the network processor and updates statistics corresponding to each rule. The network processor classifies and processes the packet in accordance with the rules and updates the internal database of the switch.

Issue group allocation circuitry controls allocation of each micro-operation to one of a plurality of issue groups, depending on detection of register conflicts between micro-operations, the register conflicts concerning access to registers of a first register set. A given micro-operation is allocated to a selected issue group for which no micro-operation already allocated to the selected issue group has a register conflict with the given micro-operation and the selected issue group is a younger issue group than any issue group already allocated an older micro-operation than the given micro-operation for which a register conflict is detected between the given micro-operation and the older micro-operation. Issue circuitry controls issue of the micro-operations based on the issue groups, to prevent any instruction in a given issue group being issued until all micro-operations in any older issue group than the given issue group have been issued.