Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.

An example SC integrator can include first and second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. The SC integrator can be configured for adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at one or more cycles of a master clock and can be configured for keeping the time distance/delay between those samples relatively small across a range of master clock frequencies.

Some embodiments include apparatuses having a first circuit portion, a second circuit portion, and a third circuit portion. The first circuit portion includes a first transistor to receive a first signal of a differential signal pair and a second transistor to receive a second signal of the differential signal pair. The second circuit portion is coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair. The third circuit portion includes a first diode-connected transistor coupled between the first output node and a second supply node and a second diode-connected transistor coupled between the second output node and the second supply node.

A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.