A multi-die device a first die containing a plurality of first die signal path elements configured to propagate a stimulus signal and a second die containing a plurality of second die signal path elements configured to propagate the stimulus signal. The multi-die device further includes an interposer configured to establish signal communication between the first die and the second die so as to deliver the stimulus signal from the plurality of first die signal path elements to the plurality of second die signal path elements to generate a propagation delay. The propagation delay is used to generate a single unified PUF response that is indicative of the authenticity of the multi-die device.

A multi-die device a first die containing a plurality of first die signal path elements configured to propagate a stimulus signal and a second die containing a plurality of second die signal path elements configured to propagate the stimulus signal. The multi-die device further includes an interposer configured to establish signal communication between the first die and the second die so as to deliver the stimulus signal from the plurality of first die signal path elements to the plurality of second die signal path elements to generate a propagation delay. The propagation delay is used to generate a single unified PUF response that is indicative of the authenticity of the multi-die device.

After installation, a device may be asleep. A light signal device may send a message to the sleeping device to wake it up. This wake-up message may comprise the light signal device sending programmed light signals, the programmed light signals in modified morse code. An authentication part may also be included in the message. The light signal device may request an authentication message from the sleeping device.

After installation, a device may be asleep. A light signal device may send a message to the sleeping device to wake it up. This wake-up message may comprise the light signal device sending programmed light signals, the programmed light signals in modified morse code. An authentication part may also be included in the message. The light signal device may request an authentication message from the sleeping device.

After installation, a device may be asleep. A light signal device may send a message to the sleeping device to wake it up. This wake-up message may comprise the light signal device sending programmed light signals, the programmed light signals in modified morse code. An authentication part may also be included in the message. The light signal device may request an authentication message from the sleeping device.

After installation, a device may be asleep. A light signal device may send a message to the sleeping device to wake it up. This wake-up message may comprise the light signal device sending programmed light signals, the programmed light signals in modified morse code. An authentication part may also be included in the message. The light signal device may request an authentication message from the sleeping device.

Fisher's exact test is efficiently computed through secure computation. It is assumed that a, b, c and d are frequencies of a 2×2 contingency table, [a], [b], [c] and [d] are secure texts of the respective frequencies a, b, c and d, and N is an upper bound satisfying a+b+c+dN. A reference frequency computation part computes a secure text ([a.sub.0], [b.sub.0], [c.sub.0], [d.sub.0]) of a combination of reference frequencies (a.sub.0, b.sub.0, c.sub.0, d.sub.0) which are integers satisfying a.sub.0+b.sub.0=a+b, c.sub.0+d.sub.0=c+d, a.sub.0+c.sub.0=a+c, and b.sub.0+d.sub.0=b+d. A number-of-patterns determination part determines integers h.sub.0 and h.sub.1 satisfying h.sub.0≤h.sub.1. A pattern computation part computes [ai]=[a.sub.0]+i, [b.sub.i]=[b.sub.0]−i, [c.sub.i]=[c.sub.0]−i and [d.sub.i]=[d.sub.0]+i for i=h.sub.0, . . . , h.sub.1, and obtains a set S={([a.sub.i], [b.sub.i], [c.sub.i], [d.sub.i])}.sub.i of secure texts of combinations of frequencies (a.sub.i, b.sub.i, c.sub.i, d.sub.i).

Fisher's exact test is efficiently computed through secure computation. It is assumed that a, b, c and d are frequencies of a 2×2 contingency table, [a], [b], [c] and [d] are secure texts of the respective frequencies a, b, c and d, and N is an upper bound satisfying a+b+c+dN. A reference frequency computation part computes a secure text ([a.sub.0], [b.sub.0], [c.sub.0], [d.sub.0]) of a combination of reference frequencies (a.sub.0, b.sub.0, c.sub.0, d.sub.0) which are integers satisfying a.sub.0+b.sub.0=a+b, c.sub.0+d.sub.0=c+d, a.sub.0+c.sub.0=a+c, and b.sub.0+d.sub.0=b+d. A number-of-patterns determination part determines integers h.sub.0 and h.sub.1 satisfying h.sub.0≤h.sub.1. A pattern computation part computes [ai]=[a.sub.0]+i, [b.sub.i]=[b.sub.0]−i, [c.sub.i]=[c.sub.0]−i and [d.sub.i]=[d.sub.0]+i for i=h.sub.0, . . . , h.sub.1, and obtains a set S={([a.sub.i], [b.sub.i], [c.sub.i], [d.sub.i])}.sub.i of secure texts of combinations of frequencies (a.sub.i, b.sub.i, c.sub.i, d.sub.i).

The invention relates to a device for generating random numbers, comprising a pair of memristors. The pair of memristors comprises a first and a second memristor, each memristor of the pair in turn comprises a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode. Each memristor is operatively connected to an output terminal by means of its bottom electrode. A control logic is connected to the memristors for applying suitable voltages necessary to determine a change of resistance in at least one memristor of the pair.

The invention relates to a device for generating random numbers, comprising a pair of memristors. The pair of memristors comprises a first and a second memristor, each memristor of the pair in turn comprises a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode. Each memristor is operatively connected to an output terminal by means of its bottom electrode. A control logic is connected to the memristors for applying suitable voltages necessary to determine a change of resistance in at least one memristor of the pair.