A pixel that emits light at brightness corresponding to the amount of a driving current regardless of a threshold voltage of a driving transistor, and secure sufficient compensation time by separating an operation of compensating for the threshold voltage of the driving transistor and an operation of writing a data signal, and a display apparatus including the pixel.

A pixel circuit includes a data writing sub-circuit and a leakage prevention sub-circuit. The data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal and a light-emitting control sub-circuit, and is configured to: in a data writing period, store a light-emitting compensation signal in response to a gate scan signal from the first scan signal terminal and a data signal from the data signal terminal; and in a light-emitting period, assist in controlling the light-emitting control sub-circuit to be turned on according to the light-emitting compensation signal. The leakage prevention sub-circuit is coupled to the data writing sub-circuit and an auxiliary voltage terminal that is configured to provide to a constant voltage, and is configured to: in the data writing period, store another light-emitting compensation signal; and in the light-emitting period, inhibit leakage of the data writing sub-circuit according to the another light-emitting compensation signal.

Display panel, light sensing detection method thereof and display device are provided. The display panel includes a plurality of light sensing detection units. A light sensing detection unit of the plurality of light sensing detection units includes a light sensing detection circuit. The light sensing detection circuit corresponding to a same light sensing detection unit includes N light sensing detection branches connected in parallel, a light sensing detection branch of the N light sensing detection branches includes a storage capacitor, and N≥2. The N light sensing detection branches include a first light sensing detection branch and a second light sensing detection branch. The storage capacitor includes a first storage capacitor located in the first light sensing detection branch and a second storage capacitor located in the second light sensing detection branch. A capacitance of the first storage capacitor is greater than a capacitance of the second storage capacitor.

A light-emitting display apparatus includes a display panel configured to display an image, a data driving circuit configured to apply a data voltage to the display panel, and a signal applying circuit configured to apply a data voltage output from a first channel of the data driving circuit to one of at least two data lines disposed on the display panel, in which the signal applying circuit includes a compensation circuit configured to prevent a data voltage increase due to signal coupling when the data voltage output from the first channel is applied to one of the at least two data lines.

A display device includes a first active layer disposed on a substrate and including a source area, a resistance area, and a drain area spaced apart from the source area by the resistance area, a first gate electrode and a second gate electrode disposed on the first active layer and overlapping the first active layer, and a first power voltage electrode disposed on the first gate electrode and the second gate electrode and overlapping the resistance area in a cross-sectional view. In this case, the resistance area of the active layer and the first power voltage electrode may form a floating node capacitor. Accordingly, in a case that the first gate electrode and the second gate electrode form a dual gate transistor with the active layer, an instantaneous voltage increase may be suppressed and current leakage may be prevented.

A display device includes a scan line extending in a direction, a data line and a driving voltage line extending in another direction, a transistor electrically connected to the driving voltage line and including a first gate electrode and a first semiconductor layer, a second transistor electrically connected to the scan and data lines and including a second gate electrode and a second semiconductor layer, a first capacitor electrically connected to the first transistor and including first and second capacitor plates, and a second capacitor including a third capacitor plate electrically connected to the first transistor and a fourth capacitor plate electrically connected to the second transistor. The second capacitor plate includes a first hole overlapping the first capacitor plate, the fourth capacitor plate includes a second hole overlapping the third capacitor plate, and a size of the second hole is different from that of the first hole.

The display device includes at least one pixel having a first capacitive element having a first terminal and a transistor connected to the first terminal and having a second terminal and a gate electrode. A driving method of the display device including in a first frame, a signal with a first pulse width is supplied to the gate electrode of the transistor, and a first voltage is written from the second terminal to the first terminal. In the second frame after the first frame, a signal with a second pulse width is supplied to the gate electrode, and the first terminal holds the first voltage. In the third frame after the second frame, a signal with a third pulse width is supplied to the gate electrode, and the second voltage is written from the second terminal to the first terminal.

A shift register unit includes a first input/output unit which includes a first pull-down control circuit and a first auxiliary input circuit, and a second input/output unit which includes a second pull-down control circuit and a second auxiliary input circuit. The first pull-down control circuit controls a level of a first pull-down node. The first auxiliary input circuit is coupled to the first pull-down control circuit and controls the first pull-down control circuit together with a level of a first pull-up node in response to a display control signal and a blanking control signal. The second pull-down control circuit controls a level of a second pull-down node. The second auxiliary input circuit is coupled to the second pull-to down control circuit and controls the second pull-down control circuit together with a level of a second pull-up node in response to the display control signal and the blanking control signal.

A pixel driving circuit includes: an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a current leakage suppression sub-circuit. The energy storage sub-circuit is coupled to a first node and a second node. The reset sub-circuit is coupled to the second node, a first scan timing signal terminal, and an initialization signal terminal. The compensation sub-circuit is coupled to the second node, a third node, and a second scan timing signal terminal. The driving sub-circuit is coupled to the second node, the third node, and a first voltage signal terminal. The current leakage suppression sub-circuit is coupled to the energy storage sub-circuit, the reset sub-circuit, and the compensation sub-circuit. The current leakage suppression sub-circuit is configured to suppress current leakage of the energy storage sub-circuit in a process of generating and transmitting the driving signal by the driving sub-circuit.

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.