A display panel and a display device are provided in the present disclosure. The display panel includes drive circuits and pixel circuits, where the drive circuits provide control signals for the pixel circuits, the pixel circuits provide drive currents for light-emitting elements of the display panel, and the drive circuits include a first drive circuit and a second drive circuit; and further includes signal line groups. The signal line groups include a first signal line group and a second signal line group. Along the second direction, a width of the first drive circuit is W1, a width of the second drive circuit is W2, a total width of the M0 signal lines in the first signal line group is D1, a total width of the N0 signal lines in the second signal line group is D2, W2>W1, D2>D1, and D2/W2>D1/W1.

A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

An image display system includes a graphic processor which generates an image signal, a control signal, and a variable frequency signal; and a display device which displays an image at a frame frequency corresponding to the variable frequency signal from the graphic processor. The display device includes pixels connected to emission control lines, data lines, and scan lines; a controller which provides reference data including information on reference cycles, which are cycles in which an emission control start signal is output, to the graphic processor, outputs the emission control start signal based on the control signal, and adjusting an output timing of a scan start signal based on the variable frequency signal; an emission driver which supplies emission control signals to the emission control lines based on the emission control start signal; and a scan driver which supplies scan signals to the scan lines based on the scan start signal.

The present disclosure relates to a driving unit. The driving unit may include a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit may include a plurality of first switching elements, and at least some of the plurality of first switching elements may be configured to output a first signal to a first output terminal of the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit may include one or more second switching elements, and at least one of the one or more second switching elements may be configured to output a second signal to a second output terminal of the driving unit in response to the control signal from the driving control circuit. The driving control circuit may be configured to output the control signal at a control signal output terminal.

A shift register and a driving method thereof, a gate drive circuit, and a display device are provided. The shift register includes: an input circuit, configured to input an input voltage provided by the input voltage terminal to an intermediate circuit under control of a first clock signal provided by the first clock signal terminal; the intermediate circuit, configured to write a second clock signal output by the second clock signal terminal or a first power signal output by the first power terminal to the intermediate output terminal as an intermediate output signal under control of the input voltage and the control circuit; and an output circuit, configured to output an output signal, a phase of which is opposite to a phase of the intermediate output signal.

A display device includes: a pixel unit having a plurality of pixels; a timing controller supplying respective scan start signals to a plurality of scan drivers and an emission start signal to an emission driver, in response to synchronization signals supplied from the outside; the emission driver supplying an emission signal to emission control lines connected to the pixels based on the emission start signal; the scan drivers supplying scan signals to the scan lines connected to the pixels based on the scan start signal; and a data driver supplying a data signal to data lines connected to the pixels, and at least one of a frequency of the emission start signal and frequencies of the scan start signals may be a first frequency that is determined independently of a driving frequency when the driving frequency is less than or equal to a threshold value.

The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.

A current-selectable light-emitting-diode (LED) display includes pixels distributed in an array of rows and columns. The pixels are grouped in mutually exclusive clusters and cluster controllers are connected to each pixel in a cluster of pixels to control the pixels in the cluster to emit light. Each cluster controller comprises a selectable current source. Each of the selectable current sources can include cluster current sources that are responsive to a current-select signal to enable one or more of the cluster current sources. The pixels can include micro-LEDs and the cluster controller can be disposed between the micro-LEDs. The display can be disposed on a display substrate with signal wires. The signal wires can include separate wire segments that are electrically connected through regeneration circuits that regenerate the signals. The display can be an information display or a backlight.

Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

A display device includes pixels including a first pixel and a second pixel sequentially disposed in a first direction, each including sub-pixels including a first electrode, a second electrode, and a light emitting element, a driving circuit including driving elements between the pixels, pixel lines connected to the pixels, and driving lines connected to the driving elements. The driving lines are in an area between the first pixel and the second pixel, and include a first driving line extending in a second direction intersecting the first direction in the area between the first pixel and the second pixel. First electrodes included in the sub-pixels of the first pixel and first electrodes included in the sub-pixels of the second pixel are spaced apart by a distance equal to or greater than a width of the first driving line in the first direction, and do not overlap the first driving line.