A fault-tolerant active matrix display device for avionics systems includes a panel glass, a set of source signal lines, and a set of gate signal lines. Each of the gate signal lines includes a first gate line end and a second gate line end on opposite sides of the panel glass. A source driver circuit is coupled to at least a portion of the source signal lines. A first gate driver circuit includes a first set of gate driver cells. Each of the gate driver cells of the first gate line driver circuit includes a gate line output connected to one of the set of gate signal lines at the first gate line end thereof. A second gate driver circuit includes a second set of gate driver cells.

A display driver integrated circuit includes a gamma circuit, a control circuit, and an output buffer circuit. The gamma circuit generates a plurality of gamma voltages based on gamma control information, a first gamma power supply voltage and a second gamma power supply voltage. The control circuit calculates a gamma limit value based on panel brightness information, voltage levels of the first and second gamma power supply voltages and the number of the plurality of gamma voltages. The control circuit generates a mode determination signal. The output buffer circuit includes a plurality of buffer circuits. Each of the plurality of buffer circuits includes an input stage and the input stage includes first transistors and second transistors. In a first driving mode, each of the plurality of buffer circuits turns off the first transistors and turns on the second transistors included in the input stage.

Disclosed are a pixel driving circuit and method, and a display device. The pixel driving circuit includes: the first port of the operation module is electrically connected via the first switch unit to the compensation wire connected to the pixel driving module, the second port of the operation module is electrically connected to the compensation wire through the second switch unit; the first switch unit is configured to transmit the driving data provided by the pixel driving module to the operation module in the self-discharge phase, and the operation module is configured to perform the calculation on the driving data in the self-discharge phase to obtain compensation data; the second switch unit is configured to write the compensation data into the pixel driving module through the compensation wire in the data writing stage.

A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LCoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

A display panel driving method, a drive circuit thereof, and a display device. The method comprises: when determined that the picture to be displayed belongs to a high power consumption display picture, providing a touch control and display integrated circuit and power supply management circuit of the display panel with a second reference voltage that is amplified by a first reference voltage and that is provided by an external voltage source, and driving each pixel to ensure the normal display of the high power consumption display picture; and when determined that the picture to be displayed belongs to a low power consumption display picture, directly providing the first reference voltage to the touch control and display integrated circuit and power supply management circuit of the display panel, and driving each pixel within the display panel so as to ensure the normal display of the low power consumption picture.

The disclosure includes multiple data drivers provided for each predetermined number of data lines. Each data driver receives an image signal; generates, based on the image signal, a positive gradation data signal and a negative gradation data signal; outputs one of the positive and negative gradation data signals to one of a first and second data line groups of a display panel; and outputs the other of the positive and negative gradation data signals to the other of the first and second data line groups. The data driver shifts a phase of the negative gradation data signal in a direction delayed with respect to the positive gradation data signal, and controls a slew rate of an output amplifier for outputting the positive gradation data signal to be lower than that of an output amplifier for outputting the negative gradation data signal.

A pixel circuit and a display device including the same are disclosed. The pixel circuit of this disclosure includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the second node; and a second switch element configured to be turned off according to a gate-off voltage of a light emitting control pulse generated in antiphase of the scan pulse.

A pixel circuit and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element discharging the second node; and a second switch element configured to supply a data voltage to the second node. The light emitting element and the first switch element are commonly connected to a VSS node to which a low-potential power supply voltage is applied.