A display panel includes a sub-pixel array, gate lines, first data lines, second data lines, a pixel control circuit and a time-division multiplexing circuit. The sub-pixel array includes a plurality of sub-pixels arranged in rows and columns. Sub-pixels in a same row are coupled to the pixel control circuit through at least one gate line. Sub-pixels located in odd-numbered rows in sub-pixels in a same column are coupled to a first data line, and sub-pixels located in even-numbered rows in the sub-pixels in the same column are coupled to a second data line. The time-division multiplexing circuit is coupled to the plurality of first data lines, the plurality of second data lines, and a data signal terminal. The time-division multiplexing circuit is configured to electrically connect the data signal terminal to the first data lines and the second data lines in a time-division manner.

A display device comprises a display panel including a plurality of data lines, a plurality of gate lines, a plurality of subpixels, and a plurality of reference voltage lines electrically connected with the plurality of subpixels, each of the plurality of subpixels including a driving transistor and a light emitting element and a gate driving circuit configured to supply a gate signal to the plurality of gate lines, wherein there are three or more periods during which a voltage change slope of a reference voltage line electrically connected with any one subpixel of the plurality of subpixels is decreased and then restored while the gate driving circuit applies the gate signal of a turn-on level voltage to the any one subpixel, thereby reducing the voltage level of the high-potential driving voltage applied to the display panel, to the minimum.

A display device comprises a display panel including a plurality of data lines, a plurality of gate lines, a plurality of subpixels, and a plurality of reference voltage lines electrically connected with the plurality of subpixels, each of the plurality of subpixels including a driving transistor and a light emitting element and a gate driving circuit configured to supply a gate signal to the plurality of gate lines, wherein there are three or more periods during which a voltage change slope of a reference voltage line electrically connected with any one subpixel of the plurality of subpixels is decreased and then restored while the gate driving circuit applies the gate signal of a turn-on level voltage to the any one subpixel, thereby reducing the voltage level of the high-potential driving voltage applied to the display panel, to the minimum.

A display device is disclosed that includes a plurality of pixels and a plurality of code pixels. The pixels include light-emitting elements, which display an image. The code pixels are disposed in the same layer as the pixels and are adjacent to a reference point disposed between the pixels. The code pixels include infrared light-emitting elements, which emit infrared light. At least one of the code pixels, disposed in a particular direction from the reference point, emit the infrared light to provide a code pattern having position information.

A display device is disclosed that includes a plurality of pixels and a plurality of code pixels. The pixels include light-emitting elements, which display an image. The code pixels are disposed in the same layer as the pixels and are adjacent to a reference point disposed between the pixels. The code pixels include infrared light-emitting elements, which emit infrared light. At least one of the code pixels, disposed in a particular direction from the reference point, emit the infrared light to provide a code pattern having position information.

A display device includes a display panel, a data driving circuit, and a timing controller, wherein the display panel includes a plurality of gate lines to which a scan signal is applied, a plurality of data lines to which a data voltage is applied, a plurality of reference voltage lines to which a reference voltage is applied, and a plurality of subpixels, wherein the data driving circuit senses a voltage on one reference voltage line selected from the plurality of reference voltage lines in a first detecting period and a second detecting period having different voltage detecting paths, and wherein the timing controller controls the data driving circuit, and determining whether or not the reference voltage line is abnormal using a sensing voltage detected from the reference voltage line.

A display device includes a display panel, a data driving circuit, and a timing controller, wherein the display panel includes a plurality of gate lines to which a scan signal is applied, a plurality of data lines to which a data voltage is applied, a plurality of reference voltage lines to which a reference voltage is applied, and a plurality of subpixels, wherein the data driving circuit senses a voltage on one reference voltage line selected from the plurality of reference voltage lines in a first detecting period and a second detecting period having different voltage detecting paths, and wherein the timing controller controls the data driving circuit, and determining whether or not the reference voltage line is abnormal using a sensing voltage detected from the reference voltage line.

A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

A display apparatus includes a substrate, a first data line in a display area, a first input line in a peripheral area, and a first connecting wire electrically connected to the first input line in a peripheral area of the substrate. The first connecting wire transfers a first input signal from the first input line to the first data line. The first connecting wire includes a first connecting line disposed in a display area of the substrate and extending in the first direction, and a second connecting line electrically connected to the first connecting line and extending in a second direction intersecting the first direction. The first connecting line and the second connecting line are disposed on different layers.