There is provided a recording apparatus, a recording method, a reproduction apparatus, a reproduction method, a recording medium, an encoding apparatus, and a decoding apparatus which enable recording or reproduction to be easily implemented at high line density. User data is encoded into a multilevel edge code, and a multilevel code whose value changes in accordance with the multilevel edge code is recorded. The multilevel edge code is generated through state transition of a code generation model which includes a state representing the number of times that zero is consecutive corresponding to a number of ways of the number of times that zero is consecutive, which is the number of times that an edge of 0 is consecutive among edges representing a change amount from an immediately preceding value of the multilevel code of an ML value which is equal to or greater than 3, and which transitions to a state representing the number of times that zero is consecutive including 0 in a case where 0 is output, and transitions to a state representing that the number of times that zero is consecutive is 0 times in a case where one of 1 to ML−1 is output.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

There is provided a recording apparatus, a recording method, a reproduction apparatus, a reproduction method, a recording medium, an encoding apparatus, and a decoding apparatus which enable recording or reproduction to be easily implemented at high line density. User data is encoded into a multilevel edge code, and a multilevel code whose value changes in accordance with the multilevel edge code is recorded. The multilevel edge code is generated through state transition of a code generation model which includes a state representing the number of times that zero is consecutive corresponding to a number of ways of the number of times that zero is consecutive, which is the number of times that an edge of 0 is consecutive among edges representing a change amount from an immediately preceding value of the multilevel code of an ML value which is equal to or greater than 3, and which transitions to a state representing the number of times that zero is consecutive including 0 in a case where 0 is output, and transitions to a state representing that the number of times that zero is consecutive is 0 times in a case where one of 1 to ML−1 is output.

The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.

The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.

Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.