A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.

A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.

A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.

A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.

A memory device which includes a control logic circuit that generates a write enable signal based on a write command, a first memory cell connected with a first word line and a first column line, a first write circuit that receives first write data to be stored in the first memory cell through a first write input/output line and applies a write voltage to a first data line based on the first write data in response to the write enable signal, and a first column multiplexer circuit that selects the first column line and connects the first column line with the first data line in response to a first column select signal, such that the write voltage is applied to the first memory cell. The first write circuit applies the write voltage to a bulk port of the first column multiplexer circuit in response to the write enable signal.

According to one embodiment, a magnetic storage device includes a nonvolatile magnetic memory including a magnetoresistance effect element capable of storing data. A magnetic sensor is configured to measure the magnitude of an external magnetic field. A controller is configured to detect errors in the data at first time intervals when the measured magnitude of the external magnetic field is less than a threshold value and to detect errors in the data at second time intervals shorter than the first time interval when the measured magnitude of the external magnetic field is equal to or greater than the threshold value.

Disclosed is a memory device including a magnetic storage element. The memory device includes a memory cell array, a voltage generator, and a write driver. The memory cell array includes a first region and a second region. The memory device is configured to store a value of a first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a programmed memory cell. The sensing circuit is configured to generate the first read current based on the value of the first read current and to perform a read operation on the first region based on the first read current.

A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The N bits represent the number of bits smaller than the N bits.