A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.

On a substrate, dynamic flash memory cell transistors and, on their outside, driving-signal processing circuit transistors are disposed. A source line wiring layer, a bit line wiring layer, a plate line wiring layer, and a word line wiring layer extend in the horizontal direction relative to the substrate and connect, from the outside of a dynamic flash memory region, in the perpendicular direction, to lead-out wiring layers on an insulating layer. The transistors in driving-signal processing circuit regions connect, via multilayered wiring layers, to upper wiring layers on the insulating layer. A high-thermal-conductivity layer is disposed over the entirety of the dynamic flash memory region and in a portion above the bit line wiring layer.

In a dynamic flash memory cell including: a HfO.sub.2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate; a HfO.sub.2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N.sup.+ layers connected to a bottom portion and a top portion of the Si pillar, and an SGT transistor including: a SiO.sub.2 layer surrounding a lower portion of a Si pillar standing on the same P-layer substrate; a HfO.sub.2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N.sup.+ layers sandwiching the HfO.sub.2 layer in a perpendicular direction and connected to a top portion and a middle portion of the Si pillar, bottom positions of the Si pillar and the Si pillar are at the same position A. A bottom portion of an upper transistor portion of the dynamic flash memory cell composed of the HfO.sub.2 layer and the TiN layer in an upper portion of the Si pillar, and a bottom portion of an SGT transistor portion composed of the HfO.sub.2 layer and the TiN layer in an upper portion of the Si pillar are at the same position B.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

A semiconductor structure comprises a gate structure of a transistor. The gate structure comprises a gate conductive portion disposed on a gate dielectric layer. The semiconductor structure further comprises a capacitor structure disposed on the gate structure. The capacitor structure comprises a first conductive layer, a dielectric layer disposed on the first conductive layer and a second conductive layer disposed on the dielectric layer. The first and second conductive layers are respectively connected to a first contact portion and a second contact portion.

A memory device includes a plurality of pages arranged in columns, each page is constituted by a plurality of memory cells arranged in rows on a substrate, the memory cells included in the page are memory cells of a plurality of semiconductor base materials that stand on the substrate in a vertical direction or that extend in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, and all memory cells included in a first page subjected to the page erase operation perform the page write operation at least once.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.