A method includes forming a plurality of first line-shaped mask patterns over a substrate including a memory cell region and an array edge region; forming a plurality of second line-shaped mask patterns over the plurality of first line-shaped mask patterns; removing first portions from the plurality of first line-shaped mask patterns in the memory cell region to leave a plurality of island-shaped mask patterns above the memory cell region; removing second portions from the plurality of first line-shaped mask patterns in the array edge region to leave a holes-provided mask pattern above the array edge region; forming a mask pattern which includes a plurality of holes provided on portions; and forming, with the mask pattern which includes the plurality of holes, a plurality of contact holes in the array edge region to provide a plurality of contact electrodes connected to a plurality of word-lines.

An n.sup.+ layer 3a connected to a source line SL at both ends, an n.sup.+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.

A capacitor structure, a semiconductor memory device including the same, a method for fabricating the same, and a method for fabricating a semiconductor device including the same are provided. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric film which is interposed between the lower electrode and the upper electrode, wherein the lower electrode includes an electrode film including a first metal element, and a doping oxide film including an oxide of the first metal element between the electrode film and the capacitor dielectric film, and the doping oxide film further includes a second metal element including at least one of Group 5 to Group 11 and Group 15 metal elements, and an impurity element including at least one of silicon (Si), aluminum (Al), zirconium (Zr) and hafnium (Hf).

The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.

Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

An apparatus includes a semiconductor substrate; an access transistor including channel, source and drain regions arranged in a vertical direction to the semiconductor substrate and a gate-electrode facing to the channel region; a storage capacitor coupled to one of the source and drain regions; a bit-line coupled to the other of the source and drain regions; and a pull-out-electrode connected to the bit-line; wherein surfaces of the source and drain regions and the pull-out-electrode on the bit-line side is arranged at substantially the same height from the upper surface of the semiconductor substrate.