A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

A pulse-width modulation (PWM) image sensor is described herein. The PWM image sensor may have a stacked configuration. A top wafer of the PWM image sensor may have a charge-to-time converter and a logic wafer, stacked with the top wafer, may include a time-to-digital converter. The PWM image sensor may utilize variable transfer functions to avoid highlight compression and may utilize non-linear time quantization. A threshold voltage, as input to a charge-to-time converter, may additionally be controlled to affect light detection, dynamic range, and other features associated with the PWM image sensor.

The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.

The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.

A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.

A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.

A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.