Patent classifications
G11C13/0016
SYSTEMS AND METHODS FOR WRITING AND READING DATA STORED IN A POLYMER
A system and method of storing and reading digital data, including providing a nanopore polymer memory (NPM) device having at least one memory cell comprising at least two addition chambers each arranged to add a unique chemical construct (or codes) to a polymer (or DNA) string when the polymer enters the respective addition chamber, the data comprising a series of codes; successively steering the polymer from deblock chambers through the nanopore into the addition chambers to add codes to the polymer to create the digital data pattern on the polymer; and accurately controlling the bit rate of the polymer using a servo controller. The device may have loading chamber(s) to load (or remove) the polymer into/from the deblock chambers through at least one “micro-hole”. The cell may be part of a memory system that stores and retrieves “raw” data and allows for remote retrieval and conversion. The cell may store multi-bit data having a plurality of states for the codes.
Magnetization alignment in a thin-film device
We disclose a magnetic device having a pair of coplanar thin-film magnetic electrodes arranged on a substrate with a relatively small edge-to-edge separation. In an example embodiment, the magnetic electrodes have a substantially identical footprint that can be approximated by an ellipse, with the short axes of the ellipses being collinear and the edge-to-edge separation between the ellipses being smaller than the size of the short axis. In some embodiments, the magnetic electrodes may have relatively small tapers that extend toward each other from the ellipse edges in the constriction area between the electrodes. Some embodiments may also include an active element inserted into the gap between the tapers and electrical leads connected to the magnetic electrodes for passing electrical current through the active element. When subjected to an appropriate external magnetic field, the magnetic electrodes can advantageously be magnetized to controllably enter parallel and antiparallel magnetization states.
SYSTEMS AND METHODS FOR WRITING AND READING DATA STORED IN A POLYMER
A system and method of storing and reading digital data, including providing a nanopore polymer memory (NPM) device having at least one memory cell comprising at least two addition chambers each arranged to add a unique chemical construct (or codes) to a polymer (or DNA) string when the polymer enters the respective addition chamber, the data comprising a series of codes; successively steering the polymer from deblock chambers through the nanopore into the addition chambers to add codes to the polymer to create the digital data pattern on the polymer; and accurately controlling the bit rate of the polymer using a servo controller. The device may have loading chamber(s) to load (or remove) the polymer into/from the deblock chambers through at least one “micro-hole”. The cell may be part of a memory system that stores and retrieves “raw” data and allows for remote retrieval and conversion. The cell may store multi-bit data having a plurality of states for the codes.
Display device with semiconductor memory cell
The present invention provides a display device including a nonvolatile memory circuit to which data can be added without increasing the number of manufacturing steps, and an electronic appliance using the display device. A display device of the present invention has a memory circuit that includes a memory element with a simple structure in which an organic compound layer is interposed between a pair of conductive layers. According to the present invention having the above mentioned structure, a display device having a nonvolatile memory circuit to which data can be added can be provided without increasing the number of manufacturing steps.
Memory devices with selective page-based refresh
Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages configured to be refreshed according to a refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.
Data storage using peptides
Methods and systems for storing digital data into peptide sequences and retrieving digital data from peptide sequences are disclosed. The method for storing digital data into peptide sequences may include: encoding the digital data into a digital code; translating the digital code into the peptide sequences; and synthesizing the translated peptide sequences. The method for retrieving digital data from peptide sequences may include: sequencing and determining an order of the peptide sequences; converting the peptide sequences with the determined order into a digital code; and decoding the digital data from the digital code. Codes with error-correction capability are developed for encoding digital data into peptide sequences, and a computational method implemented in a software is developed for sequencing the digital data bearing peptides.
Cross-point array of polymer junctions with individually-programmed conductances
Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.
Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
NEUROMORPHIC ARCHITECTURES, ACTUATORS, AND RELATED METHODS
A neuromorphic architecture is formed from a laminate of non-woven carbon fiber reinforced polymer layers arranged in a plurality of different directions. A plurality of distributed nodes are formed through the laminate via transverse voids, and an encapsulant encapsulates an electrochemical fluid or gel such that the electrochemical fluid or gel may flow within the nodes and around the laminate. Electrical current flowing through the architecture creates reversible metal deposits at various nodes, depending on the path developed through the architecture, with a complexity sufficient for neuromorphic processing, and providing a writable and erasable memory. A neuromorphic actuator may be formed by combining shape memory materials with such a neuromorphic architecture, which may provide desired surface contours and/or actuations based on current in the neuromorphic architecture. Such neuromorphic architectures and actuators may be trained according to various methods, using feed-forward and/or feedback techniques.
MEMORY DEVICES WITH SELECTIVE PAGE-BASED REFRESH
Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages configured to be refreshed according to a refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.