A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify operations. The programming operations include applying a programming voltage to the selected word line, and the verify operations include applying a verify voltage to the selected word line. At least one programming loop of the plurality of programming loops further includes a pre-verify operation. The pre-verify operation includes applying a pre-read voltage to the selected word line. The pre-read voltage is less than the verify voltage.

The present technology relates to an electronic device. According to the present technology, a memory device having improved verify accuracy may include a memory block including memory cells, a read and write circuit including a plurality of page buffers, a current sensing circuit configured to perform a verify operation of comparing sensing voltages with a reference voltage, and a control logic configured to control the current sensing circuit to perform the verify operation. The control logic controls performing a first verify operation on each of page buffer groups having a same logical group number, and performing a second verify operation on each of page buffer groups having a same physical group number, and the current sensing circuit outputs a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.

A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The program operation includes a plurality of program loops. The control logic is configured to control the peripheral circuit to apply a program voltage to a select word line that is connected to the selected memory cells, apply a first under drive voltage that is determined based on at least one verify voltage to the select word line, and apply the at least one verify voltage to the select word line in each of the plurality of program loops. The first under drive voltage is at a lower voltage level than the at least one verify voltage.

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation.

A semiconductor memory device includes a memory block including plurality of string groups, a peripheral circuit, and control logic. The peripheral circuit performs a program operation on source select transistors included in the memory block. The control logic controls the program operation of the peripheral circuit. Each of the plurality of string groups includes at least one cell string, and the at least one cell string includes inner source select transistors located adjacent to memory cells and outer source select transistors located adjacent to a common source line. The control logic controls the peripheral circuit to perform program operations on the outer source select transistors and the inner source select transistors by an ISPP method. The control logic controls the peripheral circuit to perform a verify operation by dividing the inner source select transistors into at least two groups during the program operation of the inner source select transistors.

Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.