A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.

The invention provides a storage structure and an erase method thereof, which can perform an erase operation on memory blocks B.sub.1 . . . B.sub.n, where n is an integer greater than or equal to 2. The storage structure includes a first memory bank, a second memory bank and a controller, wherein the memory blocks are sequentially alternately arranged in the first memory bank and the second memory bank. The controller is used to control the memory blocks to sequentially undergo an erase operation. The erase operation includes sequentially performing a first process and a second process. When memory block B.sub.i undergoes the second process, the memory block B.sub.i+1 undergoes the first process, where i ∈ [1, n−1].

Memory devices might include a controller configured to cause the memory device to apply a first plurality of incrementally increasing programming pulses to control gates of a particular plurality of memory cells selected for programming to respective intended data states, determine a first occurrence of a criterion being met, store a representation of a voltage level corresponding to a particular programming pulse in response to the first occurrence of the criterion being met, set a starting programming voltage for a second plurality of incrementally increasing programming pulses in response to the stored representation of the voltage level corresponding to the particular programming pulse, and apply the second plurality of incrementally increasing programming pulses to control gates of a different plurality of memory cells selected for programming to respective intended data states.

A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

Systems and methods for performing in-storage logic operations using one or more memory cell transistors and a programmable sense amplifier are described. The logic operations may comprise basic Boolean logic operations (e.g., OR and AND operations) or secondary Boolean logic operations (e.g., XOR and IMP operations). The one or more memory cell transistors may be used for storing user data during a first time period and then used for performing a logic operation during a second time period subsequent to the first time period. During the logic operation, a first memory cell transistor of the one or more memory cell transistors may be programmed with a threshold voltage that corresponds with a first input operand value and then a gate voltage bias may be applied to the first memory cell transistor during the logic operation that corresponds with a second input operand value.

A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

A memory device including: a memory cell array including a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; and a control logic configured to detect a not-open string (N/O string) from the plurality of strings in response to a write command and convert pieces of target data to be programmed on a plurality of target memory cells in the N/O string so that the pieces of target data have a value that limits a number of times a program voltage is applied to the plurality of target memory cells.

A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.

An operation method of a memory device for programming memory cells to a plurality of program states includes providing a series of program pulses to selected memory cells, performing a first verification operation of verifying a target program state among the plurality of program states, performing, when the first verification operation is passed, a second verification operation of detecting fail cells among the selected memory cells to determine if these memory cells have been overprogrammed. When the number of detected fail cells is greater than or equal to a reference value, the program operation may be terminated for that location and the data may be written to another location.

A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.