The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising:

storing in a dummy row of said memory block at least a known pattern;

performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly;

adopting the trimming parameters of the correct reading for the subsequent reading phases.

The disclosure further relates to a memory device structured for implementing the above method.

A processing device sets a first flag that indicates whether a first critical security parameter (CSP) file exists. The first CSP file includes a first set of CSPs for a memory device. The processing device sets a second flag that indicates whether the first CSP file is valid. The processing device sets a third flag that indicates whether a second CSP file exists. The second CSP file includes a second set of CSPs for the memory device. The processing device sets a fourth flag that indicates whether the second critical security parameter file is valid. The processing device selects one of the first or second CSP file as an active CSP file based on an evaluation of the first, second, third, and fourth flags.

The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.

A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.

A non-volatile memory includes: a plurality of user data storage blocks configured to store user data; a user setting storage block configured to store a bad block address table; and a controller configured to perform: executing a first erase operation on one of the plurality of user data storage blocks according to an external instruction; executing a second erase operation on the one of the plurality of user data storage blocks in response to failure of the first erase operation; marking the one of the plurality of user data storage blocks as a bad block in response to failure of the second erase operation; and updating the bad block address table stored in the user setting storage block according to the bad block newly marked. An operation method of the non-volatile memory is also provided.