When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

An apparatus is provided that includes a plurality of non-volatile memory cells and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to perform a first program-verify iteration on a first set of non-volatile memory cells coupled to a first word line to determine a first starting program voltage that programs the first set of the non-volatile memory cells to a first programmed state, and program a second set of non-volatile memory cells coupled to the first word line beginning with the first starting program voltage only if a defect condition does not exist.

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

A method for programming a memory device including a first plane and a second plane is provided. The method includes simultaneously initiating programming of the first plane and the second plane, and in response to the first plane being successfully programmed and the second plane not being successfully programmed, suspending the programming of the first plane, and keeping the programming of the second plane.

A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.

A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.

A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This reduces the amount of soft bit data. The efficient soft sense sequence can be used as a default read mode, providing soft bit information for ECC correction without triggering a read error handling flow. Merging the soft bit and hard bit sense into one sequence can avoid extra overhead for read sequence operations.

Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.

A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.