Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to determining that the first initialization vector is outside the range of valid initialization vectors, the configuration control circuit signals that the first initialization vector is invalid.

A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.

A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.

Storage devices, storage controllers, and apparatuses are provided for providing one-time writeable storage devices. In an implementation, a storage device may include a data storage medium including data storage locations and a controller. The controller is coupled to the data storage medium and is configured to receive at least write operations for storage of data onto the data storage medium. The controller is further configured to provide a write-once mode of operation that prevents the data written to ones of the data storage locations of the data storage medium from being overwritten or erased by further data directed for storage to the ones of the data storage locations.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

A storage device includes a basic memory to store a message received from an external device, a security memory to store an authentication key for authenticating the message, a controller to output a control signal, and a security engine to obtain the authentication key from the security memory with an authority to access the security memory in response to the control signal from the controller and to block an access of the controller to the security memory.