An anti-fuse circuit includes the following: a first transistor, and at least one parasitic transistor and at least one parasitic triode that are connected to the first transistor. The at least one parasitic transistor and the at least one parasitic triode are connected to a first node.

According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

A signal generation circuit includes: a clock circuit configured to receive a flag signal and generate a clock signal; a control circuit configured to generate a control circuit; and a generation circuit connected to both the clock circuit and control circuit and configured to receive the clock signal, the control signal, and the flag signal and generate a target signal, wherein when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal is maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level; and the generation circuit is further configured to determine the target duration according to the clock signal and control signal.

Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

Embodiments of the present disclosure provide a method and an apparatus of testing a word line. After repair of a memory array is completed, if a target word line in a failure state exists in the memory array, a second numerical value is written into the target word line, and then it is determined, according to a numerical value outputted by each word line in the memory array, whether there are at least two word lines in an on-state in the memory array; if there are at least two word lines in an on-state simultaneously in the memory array, a current value generated by the target word line in an on-to-off process is detected; when the current value generated by the target word line in the on-to-off process is greater than a preset current threshold, it is determined that the target word line has a repair fault.

A failure bit count (FBC) circuit for memory array is provided. The memory array includes pages each having plural sectors and a redundancy column. The FBC circuit includes FBC units, in which each FBC unit is respectively coupled to each sector for providing a failure bit count current; a redundancy FBC unit coupled to the redundancy column and provides a redundancy current; a switch having a first end and a second end capable of being switched to couple to one of outputs of the FBC units to receive the failure bit count current from one of the FBC units; a comparator having a first input end that receives a reference current, and a second input end that receives a measurement current obtained by adding the failure measurement current and the redundancy current, and an output end outputting a judge signal to indicate a number of failure bits for each sector.

A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.