Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

A semiconductor device includes a level conversion circuit. The level conversion circuit includes a first transistor, a second transistor, a current limiting element, and a voltage adjusting circuit. The first transistor includes a gate connected to an input node. A signal corresponding to a first power supply voltage is input to the input node. The second transistor has a source connected to a drain of the first transistor, a drain connected to a second power supply voltage that is higher than the first power supply voltage, and a gate connected to a first node. The current limiting element is electrically connected between the first node and an output node. The voltage adjusting circuit adjusts a voltage of the first node in accordance with the signal input to the input node.

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

A memory system in an embodiment includes: a nonvolatile memory; a memory controller configured to control the memory; and a power supply circuit configured to supply a voltage of power of at least one of the memory and the memory controller, wherein the power supply circuit is configured to: store first information having a value of the voltage to be supplied; output an output voltage based on the value of the voltage specified by the stored first information; detect an output current at an output end of the output voltage; compare a value of the detected output current with a threshold value; and update the stored first information to second information based on a result of the comparison, the second information having an updated value of the voltage to be supplied.

A storage device performs a read operation by restoring an ON cell count (OCC) from a power loss protection (PLP) area of a nonvolatile memory. The nonvolatile memory includes a memory blocks, a buffer memory and a controller. The buffer memory stores a first ON cell count (OCC1) indicating a number of memory cells turned ON by a first read voltage and a second ON cell count (OCC2) indicating a number of memory cells turned ON by a second read voltage among the memory cells connected to a reference word line. The controller stores the OCC1 for each of the memory blocks in the PLP area when a sudden power off occurs in the storage device.