An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2.sup.X−1, each having a resistance equal to R*(2.sup.Y)*i, i being an index having a value ranging from 1 to 2.sup.X−1, a first of the M resistors having a resistance of R*2.sup.Y, a last of the M resistors having a resistance of R*2.sup.Y*(2.sup.X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

A resistor material including a plurality of crystalline phases having a positive temperature coefficient of resistance, and an amorphous phase having a negative temperature coefficient of resistance and having a resistivity higher than the crystalline phase, in a mixed state, is provided. Moreover, a resistor element having a resistor film configured by the resistor material described above, and a method of manufacturing a resistor element by forming a film of an amorphous material having a negative temperature coefficient of resistance and subjecting this film to an annealing treatment to obtain the resistor element described above, are provided.

A method of tuning an electrical resistance of a laser-induced graphene heater is provided. The method includes forming a base carbon heating element, and determining a target electrical resistance of a laser-induced graphene (LIG) heater to be fabricated from the base carbon heating element. The method further includes determining a targeted LIG pattern that provides the target electrical resistance, and directing laser energy on to the base carbon heating element based on the targeted LIG pattern to form one or more LIG regions. The one or more LIG regions define a LIG pattern to from the LIG heater having the target electrical resistance.

A thermally protected metal oxide varistor includes a body, a first electrode, a thermal fuse, and a glue. The body is made up of a crystalline microstructure including zinc oxide mixed with one or more other metal oxides. The first electrode is located on one side of the body and is connected to a first lead wire. The thermal fuse is connected between the first electrode and the first lead wire. The glue is to be deposited over the thermal fuse as well as over a top portion of the first lead wire.

A method for calibrating a resistance value comprises the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the measured value of the reference capacitor. The method may more specifically comprise the steps of directing a constant current through the reference capacitor during a reference time interval; after the reference time interval, directing the constant current through the variable resistor; and varying the variable resistor value progressively by varying a control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor.

A method for calibrating a resistance value comprises the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the measured value of the reference capacitor. The method may more specifically comprise the steps of directing a constant current through the reference capacitor during a reference time interval; after the reference time interval, directing the constant current through the variable resistor; and varying the variable resistor value progressively by varying a control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor.

An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

The invention provides a method for adjusting the resistance value of a thin film resistor layer in a semiconductor structure, which comprises forming the thin film resistor layer, the material of the thin film resistor layer comprises titanium nitride, and the thin film resistor layer has an original resistance value, a mask layer with tensile force is formed above the thin film resistor layer, and the mask layer with tensile force changes a lattice size of the thin film resistor layer, so that the lattice size of the thin film resistor layer becomes larger and the original resistance value of the thin film resistor layer is reduced.

An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2.sup.X−1, each having a resistance equal to R*(2.sup.Y)*i, i being an index having a value ranging from 1 to 2.sup.X−1, a first of the M resistors having a resistance of R*2.sup.Y, a last of the M resistors having a resistance of R*2.sup.Y*(2.sup.X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.