A plasma processing apparatus includes a plasma processing chamber configured to contain a plasma comprising a plasma sheath, ions of a first species, and ions of a second species, a substrate disposed in the plasma processing chamber, and a short pulse generator coupled to the substrate, the short pulse generator configured to generate a pulse train of negative bias pulses. Each of the negative bias pulses has a pulse duration less than 10 μs. A pulse delay between successive negative bias pulses is at least five times the pulse duration. The first species has a first mass and the second species has a second mass less than the first mass. The pulse train spatially stratifies the ions of the first species and the ions of the second species in the plasma sheath.

A method of plasma processing includes generating plasma in a plasma processing chamber containing a first species, a second species, and a substrate. The plasma includes a plasma sheath, first species ions, and second species ions. The first species has a first mass and the second species has a second mass that is less than the first mass. The method further includes applying a pulse train of negative bias pulses to the substrate. Each of the negative bias pulses has a pulse duration less than 10 μs and spatially stratifies the first species ions and the second species ions in the plasma sheath. No bias voltage is applied to the substrate during a pulse delay after each negative bias pulse. The pulse delay is at least five times the pulse duration.

Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a showerhead. The chambers may include a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled with the platen along a second surface of the platen opposite the first surface of the platen. The shaft may extend at least partially through the chamber body. A coating may extend conformally about the first surface of the platen. The coating may include a first layer of silicon proximate the first surface of the platen, and may include a second layer of material overlying the first layer of silicon.

A first radiofrequency signal generator is set to generate a low frequency signal. A second radiofrequency signal generator is set to generate a high frequency signal. An impedance matching system has a first input connected to an output of the first radiofrequency signal generator and a second input connected to an output of the second radiofrequency signal generator. The impedance matching system controls impedances at the outputs of the first and second radiofrequency signal generators. An output of the impedance matching system is connected to a radiofrequency supply input of a plasma processing system. A control module monitors reflected voltage at the output of the second radiofrequency signal generator. The control module determines when the reflected voltage indicates a change in impedance along a transmission path of the high frequency signal that is indicative of a particular process condition and/or event within the plasma processing system.

A plasma processing method includes: providing a substrate including a silicon-containing film and a mask film having an opening pattern, on a substrate support; and etching the silicon-containing film using the mask film as a mask, with a plasma generated by a plasma generator provided in the chamber. The etching includes: supplying a processing gas containing one or more gases including carbon, hydrogen, and fluorine into the chamber; generating a plasma from the processing gas by supplying a source RF signal to the plasma generator; and supplying a bias RF signal to the substrate support unit. In the etching, the silicon-containing film is etched by at least hydrogen fluoride generated from the processing gas, while forming a carbon-containing film on at least a part of a surface of the mask film.

A method of manufacturing a semiconductor device includes: preparing a stacked body in which a first layer, a second layer, a third layer, and a fourth layer are stacked in this order on a semiconductor substrate in a first direction, the stacked body including a first region and a second region different from the first region; etching the fourth layer in the first region and the second region to expose the third layer by irradiating the first region and the second region with an ion beam, and etching the third layer and the second layer in the second region to expose the first layer by irradiating the second regions with an ion beam in a state where the third layer is exposed in the first region.

Methods of processing a semiconductor device structure comprise cooling an electrostatic chuck (ESC) for the semiconductor device structure, which comprises tiers of alternating materials including at least one dielectric material, to a temperature of 30 C. or less, forming an opening in the semiconductor device structure with a plasma of a gas comprising a hydrogen-based gas and a fluorine-based gas in which the hydrogen-based gas comprises between about 10 vol % and 90 vol %. Other methods of processing a semiconductor device structure comprise cooling an ESC for the semiconductor device structure to a temperature of 30 C. or less, applying a low frequency radio frequency (RF) having a non-sinusoidal waveform to the ESC, and forming an opening in the semiconductor device structure with a generated plasma. A processing system includes an ESC, a coolant system, and a low frequency RF power source generating a non-sinusoidal waveform comprising a combination of multiple sinusoidal waveforms.

Provided are a plasma processing apparatus with a radio-frequency power supply supplying temporally modulated intermittent radio-frequency power which can be controlled with high precision in a wide repetition frequency band, and a plasma processing method using the plasma processing apparatus. A plasma processing apparatus includes: a vacuum vessel; a plasma generating section plasma in the vacuum vessel; a stage installed in the vacuum vessel and mounted with a sample; and a radio-frequency power supply applying temporally modulated intermittent radio-frequency power to the stage, wherein the radio-frequency power supply has two or more different frequency bands and temporally modulates the radio-frequency power by a repetition frequency which has the same range of analog signals used in each of the frequency band.

Methods of processing a semiconductor device structure comprise cooling an electrostatic chuck (ESC) for the semiconductor device structure, which comprises tiers of alternating materials including at least one dielectric material, to a temperature of 30 C. or less, forming an opening in the semiconductor device structure with a plasma of a gas comprising a hydrogen-based gas and a fluorine-based gas in which the hydrogen-based gas comprises between about 10 vol % and 90 vol %. Other methods of processing a semiconductor device structure comprise cooling an ESC for the semiconductor device structure to a temperature of 30 C. or less, applying a low frequency radio frequency (RF) having a non-sinusoidal waveform to the ESC, and forming an opening in the semiconductor device structure with a generated plasma. A processing system includes an ESC, a coolant system, and a low frequency RF power source generating a non-sinusoidal waveform comprising a combination of multiple sinusoidal waveforms.

Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.