A radio frequency (RF) power generation system includes a RF power source that generates a RF output signal delivered to a load. A RF power controller is configured to generate a control signal to vary the RF output signal. The controller adjusts a parameter associated with the RF output signal, and the parameter is controlled in accordance with a trigger signal. The parameter is adjusted in accordance with a cost function, and the cost function is determined by intruding a perturbation into an actuator that affects the cost function. The actuator may control an external RF output signal, and the trigger signal may vary in accordance with the external RF output signal.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing layer on surfaces defining the processing region of the semiconductor processing chamber. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber.

An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.

Processing methods and apparatus for depositing a protective layer on internal surfaces of a reaction chamber are provided. One method may include depositing, while no wafers are present in the reaction chamber having interior surfaces, a first layer of protective material onto the interior surfaces, the interior surfaces comprising a first material, processing, after the depositing the first layer, a portion of a batch of wafers within a reaction chamber, measuring an amount of the first material in the reaction chamber during processing the portion of the batch of wafers, or on one of the wafers in the portion of the batch of wafers, determining that the first amount exceeds a threshold, and depositing, in response to determining that the first amount exceeds the threshold and while no wafers are present in the reaction chamber, a second layer of protective material onto the interior surfaces of the reaction chamber.

A heater controller controls power supplied to a heater capable of adjusting the temperature of a placement surface such that the heater reaches a set temperature. A temperature monitor measures the power supplied in the non-ignited state where the plasma is not ignited and in the transient state where the power supplied to the heater decreases after the plasma is ignited, while the power is controlled such that the temperature of the heater becomes constant. A parameter calculator calculates a heat input amount and the thermal resistance by using the power supplied in the non-ignited state and in the transient state to perform a fitting on a calculation model for calculating the power supplied in the transient state. A set temperature calculator calculates the set temperature of the heater at which the wafer reaches the target temperature, using the heat input amount and thermal resistance.

A method of detecting and classifying anomalies during semiconductor processing includes executing a wafer recipe a semiconductor processing system to process a semiconductor wafer; monitoring sensor outputs from a sensors that monitor conditions associated with the semiconductor processing system; providing the sensor outputs to models trained to identify when the conditions associated with the semiconductor processing system indicate a fault in the semiconductor wafer; receiving an indication of a fault from at least one of the models; and generating a fault output in response to receiving the indication of the fault.

An impedance measurement jig may include a first contact plate, a second contact plate, a cover plate, a plug, and an analyzer. The first contact plate may make electrical contact with an ESC in a substrate-processing apparatus. The second contact plate may make electrical contact with a focus ring configured to surround the ESC. The cover plate may be configured to cover an upper surface of the substrate-processing apparatus. The plug may be installed at the cover plate to selectively make contact with the first contact plate or the second contact plate. The analyzer may individually apply a power to the first contact plate and the second contact plate through the plug to measure an impedance of the ESC and an impedance of the focus ring. Thus, the impedances of the ESC and the focus ring may be individually measured to inspect the ESC and/or the focus ring.

A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.

In one embodiment, a semiconductor manufacturing apparatus includes an electrostatic chuck that includes a base and a first electrode provided on the base and is configured to electrostatically adsorb a wafer on the first electrode. The apparatus further includes a measurement module configured to measure potential of the wafer. The apparatus further includes a controller configured to adjust potential of the base based on the potential of the wafer and to adjust potential of the first electrode based on the potential of the wafer or the base, when the potential of the wafer measured by the measurement module changes.

Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.